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    • 5. 发明授权
    • OPU frame generating device and OPU frame test device
    • OPU帧生成装置和OPU帧测试装置
    • US09065581B2
    • 2015-06-23
    • US13433370
    • 2012-03-29
    • Takashi FuruyaTsuyoshi Ogawa
    • Takashi FuruyaTsuyoshi Ogawa
    • H04J3/16H04J3/14
    • H04J3/1652H04J3/14H04J2203/0073
    • An OPU frame generating device includes a frequency setting unit that sets a frequency corresponding to a bit rate of data which can be stored in a payload area, a parameter calculating unit that calculates a parameter Cm indicating an integer part of the amount of data included in the payload area using the set frequency, a data inserting unit that outputs a timing signal determined by the parameter Cm and inserts data at a position determined by the parameter Cm in the payload area, a data generating unit that generates data in synchronization with the timing signal, and a frame generating unit that generates an OPU frame having the payload area into which the data is inserted.
    • OPU帧产生装置包括:频率设定单元,其设定与能够存储在有效载荷区域中的数据的比特率对应的频率;参数计算单元,计算表示包含在数据量的数据量的整数部分的参数Cm 使用设定频率的有效负载区域,输出由参数Cm确定的定时信号并在由有效载荷区域中的参数Cm确定的位置插入数据的数据插入单元,与定时同步地生成数据的数据生成单元 信号和帧生成单元,其生成具有插入数据的有效载荷区域的OPU帧。
    • 6. 发明授权
    • M-sequence generator, providing method thereof, and random error generating device in which M-sequence generator is used
    • M序列发生器,其提供方法以及使用M序列发生器的随机误差产生装置
    • US08433740B2
    • 2013-04-30
    • US12769341
    • 2010-04-28
    • Takashi FuruyaMasahiro KurodaKazuhiko Ishibe
    • Takashi FuruyaMasahiro KurodaKazuhiko Ishibe
    • G06F7/00G06F1/02
    • H03K3/84G06F7/584H04J13/00
    • An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(α1k), (α2k), (α3k), . . . } falls within a maximum period (2m−1), the group being produced as an element (αk) obtained by raising a root α of a polynomial to a specified power value k (k≧2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (αk) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (αk), the gate supplies the multiplication result as feedback bit data to the respective registers.
    • M序列发生器包括异或门,以响应于时钟从M个串联寄存器向寄存器反馈位数据。 循环群{(α1k),(α2k),(α3k))的周期。 。 。 }落在最大周期(2m-1)内,该组被作为通过将多项式的根α提高到具有多项式中的项的指定功率值k(k> = 2)而获得的元素(alphak) 的伽罗瓦域GF(2m)。 在包括门的乘法单元中,当将元素(alphak)馈送到另一端时,位数据被送入乘法单元的一端。 乘法单元在每个比特数据和元素(alphak)之间执行Galois域乘法,门将乘法结果作为反馈比特数据提供给各个寄存器。
    • 8. 发明申请
    • ERROR ADDITION APPARATUS
    • 错误添加装置
    • US20100174971A1
    • 2010-07-08
    • US12683072
    • 2010-01-06
    • Takashi Furuya
    • Takashi Furuya
    • H03M13/09G06F11/10
    • H04L1/0079
    • An error addition apparatus receives a data signal D having a frame format having a specific signal inserted into its front, adds errors to the data signal D, and outputs a resulting signal. The apparatus has an error addition regulation unit for receiving a frame synchronization signal F, indicative of a timing at which the front of the frame of the data signal has been inputted, and regulating the errors such that the errors are added to positions other than a region of the specific signal. Accordingly, errors are not added to a specific signal.
    • 错误添加装置接收具有插入其前端的特定信号的帧格式的数据信号D,将错误加到数据信号D上,并输出结果信号。 该装置具有误差附加调节单元,用于接收表示数据信号的帧的前部已被输入的定时的帧同步信号F,并且调整误差使得误差被添加到除 区域的具体信号。 因此,不向特定信号添加错误。