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1. 发明授权

US5343354A Stacked trench capacitor and a method for making the same 失效
标题翻译：堆叠沟槽电容器及其制造方法
公开(公告)号：US5343354A
公开(公告)日：1994-08-30
申请号：US74892
申请日：1993-06-11
申请人： Tae-woo Lee , Seon-jun Kim , Yang-ku Lee
发明人： Tae-woo Lee , Seon-jun Kim , Yang-ku Lee
IPC分类号： H01L27/108 , H01L29/94 , H01G4/10
CPC分类号： H01L29/945 , H01L27/10835
摘要： A stacked trench capacitor including a first trench formed in a semiconductor substrate, an insulating material, preferably BPSG, substantially filling the first trench to thereby define an isolation region of the substrate, a second trench formed in the first trench, the second trench being much narrower and shallower than the first trench, a storage electrode formed on the sidewalls and bottom surface of the second trench, a thin dielectric film formed on the storage electrode, and a plate electrode formed on the thin dielectric film. In a preferred embodiment, the isolation region serves to separate and electrically isolate adjacent memory cells of a semiconductor memory device, each of the memory cells including a MOSFET transistor and a stacked trench capacitor constructed as described above. An impurity region is formed in the substrate adjacent an outer sidewall of the second trench to a depth preferably substantially equal to that of the second trench, the conductivity type of the impurity region being opposite that of the substrate. An upper portion of the impurity region preferably serves as the source region of the MOSFET transistor of the memory cell.
摘要翻译：一种叠层沟槽电容器，包括形成在半导体衬底中的第一沟槽，优选为BPSG的绝缘材料，基本上填充所述第一沟槽，从而限定所述衬底的隔离区，形成在所述第一沟槽中的第二沟槽，比第一沟槽窄且浅，形成在第二沟槽的侧壁和底表面上的存储电极，形成在存储电极上的薄电介质膜和形成在薄介电膜上的板电极。在优选实施例中，隔离区域用于分离和电隔离半导体存储器件的相邻存储单元，每个存储器单元包括MOSFET晶体管和如上所述构成的层叠沟槽电容器。在衬底中邻近第二沟槽的外侧壁形成杂质区，其深度优选地基本上等于第二沟槽的深度，杂质区的导电类型与衬底相反。杂质区的上部优选用作存储单元的MOSFET晶体管的源极区。

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