专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07445992B2 Method for fabricating cell structure of non-volatile memory device 失效
标题翻译：非易失性存储器件单元结构的制造方法
公开(公告)号：US07445992B2
公开(公告)日：2008-11-04
申请号：US11281471
申请日：2005-11-18
申请人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
发明人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.
摘要翻译：使用氮化物层作为浮动栅极隔离物的非易失性存储器件的单元结构包括形成在半导体衬底上的栅极堆叠和浮置栅极晶体管。栅极堆叠包括浮置栅极的第一部分，形成在浮置栅极的第一部分上的控制栅极以及与浮动栅极的第一部分的侧壁相邻的非氮化物间隔物。浮栅晶体管包括浮置栅极的第二部分，其基本上与衬底中形成的源极和/或漏极重叠。将紫外线施加到编程单元的非氮化物间隔物可能导致浮栅的第二部分放电，从而容易地擦除编程的单元。

2. 发明授权

US07120080B2 Dual port semiconductor memory device 有权
标题翻译：双端口半导体存储器件
公开(公告)号：US07120080B2
公开(公告)日：2006-10-10
申请号：US10751178
申请日：2004-01-02
申请人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
发明人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
IPC分类号： G11C8/00 , G11C5/06 , G11C11/00 , G06F12/00 , G06F13/28
CPC分类号： H01L27/1104 , G09G3/3611 , G11C7/02 , G11C8/16 , G11C11/4125 , H01L27/11
摘要： A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.
摘要翻译：提供了包括PMOS扫描晶体管的双端口半导体存储器件。双端口半导体存储器件包括两个PMOS晶体管，两个NMOS下拉晶体管，两个NMOS传输晶体管和PMOS扫描晶体管。作为PMOS的扫描晶体管，可以提高噪声容限。此外，这七个晶体管排列在两个n阱和2个p阱中，而n阱和p阱以串联和交替的方式排列。因此，沿着存储单元的短轴的存储单元的长度相对较短。该存储单元布局通过将一对位线与阱边界并排布置，即在存储单元的短轴方向上有助于缩短位线的长度，并且可以防止位线与位线之间的串扰通过在位线和互补位线之间布置导线来补充位线。

3. 发明申请

US20060076608A1 Cell structure of non-volatile memory device and method for fabricating the same 失效
标题翻译：非易失性存储器件的单元结构及其制造方法
公开(公告)号：US20060076608A1
公开(公告)日：2006-04-13
申请号：US11281471
申请日：2005-11-18
申请人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
发明人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.
摘要翻译：使用氮化物层作为浮动栅极隔离物的非易失性存储器件的单元结构包括形成在半导体衬底上的栅极堆叠和浮置栅极晶体管。栅极堆叠包括浮置栅极的第一部分，形成在浮置栅极的第一部分上的控制栅极以及与浮动栅极的第一部分的侧壁相邻的非氮化物间隔物。浮栅晶体管包括浮置栅极的第二部分，其基本上与衬底中形成的源极和/或漏极重叠。将紫外线施加到编程单元的非氮化物间隔物可能导致浮栅的第二部分放电，从而容易地擦除编程的单元。

4. 发明授权

US06995421B2 Cell structure of non-volatile memory device and method for fabricating the same 失效
公开(公告)号：US06995421B2
公开(公告)日：2006-02-07
申请号：US10621571
申请日：2003-07-18
申请人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
发明人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hyung Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

5. 发明授权

US08587045B2 Nonvolatile memory device and method of forming the same 有权
公开(公告)号：US08587045B2
公开(公告)日：2013-11-19
申请号：US13181700
申请日：2011-07-13
申请人： Oh-Kyum Kwon , Tae-Jung Lee , Kyoung-Eun Uhn , Byung-Sun Kim
发明人： Oh-Kyum Kwon , Tae-Jung Lee , Kyoung-Eun Uhn , Byung-Sun Kim
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/78 , H01L27/11519 , H01L27/11521 , H01L27/11529 , H01L27/11558 , H01L29/94
摘要： A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.

6. 发明授权

US07330392B2 Dual port semiconductor memory device 有权
标题翻译：双端口半导体存储器件
公开(公告)号：US07330392B2
公开(公告)日：2008-02-12
申请号：US11470826
申请日：2006-09-07
申请人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hung Lee
发明人： Tae-Jung Lee , Byung-Sun Kim , Joon-Hung Lee
IPC分类号： G11C8/00
CPC分类号： H01L27/1104 , G09G3/3611 , G11C7/02 , G11C8/16 , G11C11/4125 , H01L27/11
摘要： A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.
摘要翻译：提供了包括PMOS扫描晶体管的双端口半导体存储器件。双端口半导体存储器件包括两个PMOS晶体管，两个NMOS下拉晶体管，两个NMOS传输晶体管和PMOS扫描晶体管。作为PMOS的扫描晶体管，可以提高噪声容限。此外，这七个晶体管排列在两个n阱和2个p阱中，而n阱和p阱以串联和交替的方式排列。因此，沿着存储单元的短轴的存储单元的长度相对较短。该存储单元布局通过将一对位线与阱边界并排布置，即在存储单元的短轴方向上有助于缩短位线的长度，并且可以防止位线与位线之间的串扰通过在位线和互补位线之间布置导线来补充位线。

7. 发明申请

US20120037971A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20120037971A1
公开(公告)日：2012-02-16
申请号：US13181700
申请日：2011-07-13
申请人： Oh-Kyum Kwon , Tae-Jung Lee , Kyoung-Eun Uhn , Byung-Sun Kim
发明人： Oh-Kyum Kwon , Tae-Jung Lee , Kyoung-Eun Uhn , Byung-Sun Kim
IPC分类号： H01L29/78 , H01L27/06 , H01L29/94
CPC分类号： H01L29/78 , H01L27/11519 , H01L27/11521 , H01L27/11529 , H01L27/11558 , H01L29/94
摘要： A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.
摘要翻译：非易失性存储器件具有通过器件隔离层在衬底中限定的第一有源区和第二有源区，设置在第一有源区上并包括第一电极图的金属氧化物半导体场效应晶体管（MOSFET）金属氧化物硅（MOS）电容器，其设置在第二有源区并且包括第二电极图案，并且其中第一电极图案在MOSFET的沟道的宽度方向上比第一有源区域窄。

8. 发明授权

US08772652B2 Keypad assembly for portable terminal 有权
标题翻译：便携式终端的键盘组件
公开(公告)号：US08772652B2
公开(公告)日：2014-07-08
申请号：US13117268
申请日：2011-05-27
申请人： Byung-Sun Kim , Min-Su Jung , Cheol-Hee Kim
发明人： Byung-Sun Kim , Min-Su Jung , Cheol-Hee Kim
IPC分类号： H01H9/26
CPC分类号： H01H13/705 , H01H2221/056 , H01H2223/036 , H01H2231/022 , H01H2233/03 , H04M1/23
摘要： A keypad assembly includes an operation member deformed according to user's manipulation to operate key switches, a binding member disposed on a top surface of the operation member, binding pieces extending and bent from the binding member to enclose sides of the operation member on an edge of the binding member, and a manipulation member disposed on a top surface of the binding member, the manipulation member including at least one key tops, in which the binding members are bound onto inner side walls of a housing of the portable terminal.
摘要翻译：键盘组件包括根据用户的操纵而变形以操作键开关的操作构件，设置在操作构件的顶表面上的装订构件，从装订构件延伸和弯曲的绑定件，以将操作构件的侧面包围在操作构件的边缘上装订构件和设置在装订构件的顶表面上的操纵构件，操纵构件包括至少一个键顶，其中装订构件被绑定到便携式终端的壳体的内侧壁上。

9. 发明申请

US20130208090A1 HIERARCHICAL BROADCASTING SYSTEM AND METHOD FOR 3D BROADCASTING 审中-公开
标题翻译：用于3D广播的分层广播系统和方法
公开(公告)号：US20130208090A1
公开(公告)日：2013-08-15
申请号：US13881141
申请日：2010-10-26
申请人： Keun-Sik Lee , Byung-Sun Kim , Chang-Seob Park , Sang-Jin Hahm , In-Joon Cho , Jun-Yong Lee
发明人： Keun-Sik Lee , Byung-Sun Kim , Chang-Seob Park , Sang-Jin Hahm , In-Joon Cho , Jun-Yong Lee
IPC分类号： H04N13/00
CPC分类号： H04N13/194 , H04N13/161 , H04N13/167 , H04N21/4622 , H04N21/631 , H04N21/816
摘要： Disclosed are a hierarchical broadcasting system and method for 3D broadcasting. A hierarchical 3D image broadcasting method comprises: allowing a broadcast transmission system to transmit first broadcast data for an existing broadcast to a broadcast reception system via a first communication network; and allowing the broadcast transmission system to transmit second broadcast data for 3D image broadcasting to the broadcast reception system via a second communication network. At this point, the broadcast reception system enables the first and second broadcast data to be combined in order to display a 3D image broadcast.
摘要翻译：公开了一种用于3D广播的分级广播系统和方法。分层3D图像广播方法包括：允许广播传输系统经由第一通信网络向广播接收系统发送用于现有广播的第一广播数据; 并且允许广播传输系统经由第二通信网络向广播接收系统发送用于3D图像广播的第二广播数据。此时，广播接收系统能够组合第一和第二广播数据，以便显示3D图像广播。

10. 发明申请

US20080035986A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080035986A1
公开(公告)日：2008-02-14
申请号：US11834129
申请日：2007-08-06
申请人： Sang-Soo Kim , Byung-Sun Kim
发明人： Sang-Soo Kim , Byung-Sun Kim
IPC分类号： H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A method of fabricating a semiconductor device having a non-volatile memory cell includes forming an insulation layer as an uppermost/outermost portion of the memory cell to enhance the charge retention capability of the memory cell. The insulation layer is formed after the gate structure and integrate dielectric of the non-volatile memory cell, and a gate of a logic transistor are formed. The insulation layer thus enhances the function of the intergate dielectric. Subsequently, a conductive layer is formed on the substrate including over the gate of the logic transistor. A silicide layer is then formed on the gate of the logic transistor and on the substrate adjacent opposite sides of the gate. The insulation layer thus also serves prevent the formation of a silicide layer on the non-volatile memory cell.
摘要翻译：制造具有非易失性存储单元的半导体器件的方法包括形成作为存储单元的最上部/最外部的绝缘层，以提高存储单元的电荷保持能力。在栅极结构之后形成绝缘层并且整合非易失性存储单元的电介质，并且形成逻辑晶体管的栅极。因此，绝缘层增强了隔间电介质的功能。随后，在包括在逻辑晶体管的栅极上的衬底上形成导电层。然后在逻辑晶体管的栅极上和邻近栅极的相对侧的衬底上形成硅化物层。因此，绝缘层也用于防止在非易失性存储单元上形成硅化物层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式