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1. 发明授权

US5752182A Hybrid IC 失效
标题翻译：混合集成电路
公开(公告)号：US5752182A
公开(公告)日：1998-05-12
申请号：US433926
申请日：1995-05-02
申请人： Tadayoshi Nakatsuka , Junji Itoh , Shinji Yamamoto , Mitsuru Nishitsuji
发明人： Tadayoshi Nakatsuka , Junji Itoh , Shinji Yamamoto , Mitsuru Nishitsuji
IPC分类号： H01L23/64 , H01L25/16 , H03F3/195 , H05K1/16 , H05K3/40 , H04B1/28
CPC分类号： H03F3/195 , H01L23/645 , H01L23/647 , H01L25/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/15159 , H01L2924/15162 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/165 , H05K3/403
摘要： On a ceramic substrate, spiral-type inductors of a single layer wiring of a metal thin film are provided and respectively connected to a wiring pattern formed on another face of the substrate via through holes. A semiconductor chip is flip-chip mounted on the substrate in a face-down manner. On the face of the semiconductor chip, capacitors composed of a highly dielectric material, resistors formed by an ion implantation method or a thin-film forming method, and FETs are provided, respectively. Interconnection between the substrate and an external circuit board is achieved employing terminals formed at end faces of the substrate. The terminals have a concave shape with respect to the end face of the substrate. Thus, there is no need to use a package, and miniaturization and reduction in cost of a high-performance hybrid IC is achieved.
摘要翻译：在陶瓷基板上，设置金属薄膜的单层布线的螺旋型电感器，并分别通过通孔与形成在基板的另一面上的布线图案连接。半导体芯片以面朝下的方式倒装安装在基板上。在半导体芯片的表面上，分别提供由高介电材料构成的电容器，通过离子注入法形成的电阻或薄膜形成方法以及FET。使用在基板的端面形成的端子来实现基板与外部电路基板之间的互连。端子相对于基板的端面具有凹形。因此，不需要使用封装，并且实现了高性能混合IC的小型化和降低成本。

2. 发明授权

US06570464B1 High frequency apparatus 失效
标题翻译：高频设备
公开(公告)号：US06570464B1
公开(公告)日：2003-05-27
申请号：US09648498
申请日：2000-08-25
申请人： Mitsuru Tanabe , Mitsuru Nishitsuji , Yoshiharu Anda
发明人： Mitsuru Tanabe , Mitsuru Nishitsuji , Yoshiharu Anda
IPC分类号： H01P500
CPC分类号： H01P3/003 , H01P11/003
摘要： A high frequency apparatus includes a dielectric substrate having a surface including a first area and at least one second area; a first dielectric thin layer provided on a portion of a first area; and a uniplanar transmission line provided on the first dielectric thin layer and on a portion of the second area, the uniplanar transmission line extending, continuously on the second area and the first dielectric thin layer.
摘要翻译：高频装置包括具有包括第一区域和至少一个第二区域的表面的电介质基板; 设置在第一区域的一部分上的第一电介质薄层; 以及设置在所述第一电介质薄层上和所述第二区域的一部分上的所述单面传输线，所述单面传输线在所述第二区域和所述第一电介质薄层上连续地延伸。

3. 发明授权

US06300190B1 Method for fabricating semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US06300190B1
公开(公告)日：2001-10-09
申请号：US09452389
申请日：1999-12-01
申请人： Mitsuru Nishitsuji , Yoshiharu Anda , Katsuhiko Kawashima , Tsuyoshi Tanaka
发明人： Mitsuru Nishitsuji , Yoshiharu Anda , Katsuhiko Kawashima , Tsuyoshi Tanaka
IPC分类号： H01L218242
CPC分类号： H01L29/66863 , H01L21/28587 , H01L27/0629
摘要： First, an insulating film is formed over the entire surface of a semiconductor substrate including a channel region for a field effect transistor. The insulating film has a gate electrode opening over the channel region. Next, a protective film is deposited over the entire surface of the insulating film. Then, a lower electrode, a capacitive insulating film and an upper electrode are formed in this order in a region on the protective film where a capacitor will be formed. Subsequently, part of the protective film, with which the gate electrode opening of the insulating film has been filled in, is removed, thereby exposing the semiconductor substrate within the gate electrode opening. And then a gate electrode is formed to fill in the gate electrode opening again.
摘要翻译：首先，在包括场效应晶体管的沟道区域的半导体衬底的整个表面上形成绝缘膜。绝缘膜具有在沟道区域上开口的栅电极。接下来，在绝缘膜的整个表面上沉积保护膜。然后，在保护膜上将形成电容器的区域中，依次形成下电极，电容绝缘膜和上电极。随后，去除绝缘膜的栅电极开口已经填充的保护膜的一部分，从而使半导体衬底暴露在栅电极开口内。然后形成栅电极以再次填充栅电极开口。

4. 发明授权

US5585655A Field-effect transistor and method of manufacturing the same 失效
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US5585655A
公开(公告)日：1996-12-17
申请号：US517435
申请日：1995-08-21
申请人： Yorito Ota , Katsunori Nishii , Mitsuru Nishitsuji , Hiroyuki Masato , Hiromasa Fujimoto
发明人： Yorito Ota , Katsunori Nishii , Mitsuru Nishitsuji , Hiroyuki Masato , Hiromasa Fujimoto
IPC分类号： H01L21/335 , H01L29/10 , H01L29/47 , H01L29/812 , H01L29/80
CPC分类号： H01L29/66462 , H01L29/1029 , H01L29/475 , H01L29/8128
摘要： On a semi-insulating substrate is formed a conductive layer and an undoped layer. On specified regions of the conductive layer are formed ohmic electrodes, each serving as a source electrode or a drain electrode, via a pair of square contact regions. The circumferential edges of the contact regions are undercut beneath the ohmic electrodes. Between the pair of contact regions on the conductive layer is formed a gate electrode by self alignment using the ohmic electrodes as a mask. The gate electrode has extended in the direction of gate width and the extended portion serves as a withdrawn portion of the gate electrode. Upper electrodes are formed by self alignment in the same process in which the gate electrode is formed.
摘要翻译：在半绝缘基板上形成导电层和未掺杂层。在导电层的指定区域上形成欧姆电极，每个电极用作源电极或漏电极，经由一对正方形接触区域。接触区域的圆周边缘在欧姆电极之下被切下。通过使用欧姆电极作为掩模的自对准，在导电层上的一对接触区域之间形成栅电极。栅电极在栅极宽度方向上延伸，并且延伸部分用作栅电极的退出部分。上电极通过在其中形成栅电极的相同工艺中的自对准形成。

5. 发明申请

US20060237753A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060237753A1
公开(公告)日：2006-10-26
申请号：US11388545
申请日：2006-03-24
申请人： Yoshiharu Anda , Akiyoshi Tamura , Mitsuru Nishitsuji
发明人： Yoshiharu Anda , Akiyoshi Tamura , Mitsuru Nishitsuji
IPC分类号： H01L31/112
CPC分类号： H01L29/7784 , H01L21/28575 , H01L21/28587 , H01L29/66462
摘要： A field effect transistor according to the present invention includes a channel layer formed above a semi-insulating substrate, a Schottky layer formed above the channel layer, a gate electrode formed on the Schottky layer, Ohmic contact layers that are located above the Schottky layer with the gate electrode interposed therebetween and formed of InGaAs, and a source electrode and a drain electrode that are formed on the Ohmic contact layers. The source electrode, the drain electrode and the gate electrode have a layered structure in which their corresponding layers are formed of the same material, a lowermost layer is a WSi layer and a layer containing Al is provided above the lowermost layer. A field effect transistor that has an electrode resistance equivalent to a conventional level and can reduce a cost of manufacturing a field effect transistor and a method for manufacturing the same are provided.
摘要翻译：根据本发明的场效应晶体管包括形成在半绝缘衬底上的沟道层，形成在沟道层上方的肖特基层，形成在肖特基层上的栅电极，位于肖特基层上方的欧姆接触层，介于其间并由InGaAs形成的栅电极以及形成在欧姆接触层上的源电极和漏电极。源电极，漏电极和栅电极具有层叠结构，其相应的层由相同的材料形成，最下层是WSi层，并且在最下层上设置含有Al的层。提供具有等同于常规水平的电极电阻并且可以降低制造场效应晶体管的成本的场效应晶体管及其制造方法。

6. 发明授权

US06548838B1 Field-effect transistor, bipolar transistor, and methods of fabricating the same 失效
标题翻译：场效应晶体管，双极晶体管及其制造方法
公开(公告)号：US06548838B1
公开(公告)日：2003-04-15
申请号：US09666157
申请日：2000-09-19
申请人： Yoshiharu Anda , Mitsuru Nishitsuji , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Yoshiharu Anda , Mitsuru Nishitsuji , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L310328
CPC分类号： H01L29/66462 , H01L29/41725 , H01L29/7784
摘要： A field-effect transistor of the present invention has first semiconductor layers disposed in at least two regions located above a substrate and spaced apart in a direction parallel to a substrate surface, second semiconductor layers disposed on the respective first semiconductor layers to protrude from the respective side surfaces of the first semiconductor layers, and ohmic electrodes disposed on the respective second semiconductor layers. The field-effect transistor also has a gate electrode formed by self alignment relative to the ohmic electrodes, which is disposed in a region located above the substrate and lying between the first semiconductor layers in spaced relation to the respective side surfaces of the first semiconductor layers.
摘要翻译：本发明的场效应晶体管具有位于基板上方的至少两个区域中的第一半导体层，并且在平行于衬底表面的方向上间隔开，第二半导体层设置在相应的第一半导体层上以从相应的第一半导体层的侧表面和设置在相应的第二半导体层上的欧姆电极。场效应晶体管还具有通过相对于欧姆电极进行自对准而形成的栅电极，该欧姆电极设置在位于衬底上方的区域中，并且位于第一半导体层之间，与第一半导体层的相应侧表面间隔开。

7. 发明授权

US5440174A Plurality of passive elements in a semiconductor integrated circuit and semiconductor integrated circuit in which passive elements are arranged 失效
标题翻译：在其中布置无源元件的半导体集成电路中的多个无源元件
公开(公告)号：US5440174A
公开(公告)日：1995-08-08
申请号：US73907
申请日：1993-06-09
申请人： Mitsuru Nishitsuji
发明人： Mitsuru Nishitsuji
IPC分类号： H01L21/70 , H01L27/06 , H01L23/48 , H01L27/02 , H01L29/40 , H01L29/68
CPC分类号： H01L27/0688 , H01L21/707 , H01L2924/0002
摘要： A method consists of the steps of depositing a Ti--Pt metal film on a SiN layer insulation film mounted on GaAs substrate, etching the Ti--Pt metal film to form a first metal layer, depositing a SrTiO.sub.3 insulating film, etching the SrTiO.sub.3 insulating film to form an insulating film, depositing a WSiN metal film according to a sputtering technique while controlling a deposition pressure of nitrogenous gas, etching the WSiN metal film to simultaneously form a second metal layer on the insulating film and a thin metal film resistive element on the SiN layer insulation film, depositing a SiO.sub.2 passivation film, and making via holes. SrTiO.sub.3 has a high relative dielectric constant, and WSiN has a high melting point. Nitrogen atoms in WSiN prevent oxygen atoms in the insulating film from diffusing into the second metal layer. The adhesion of second metal film to the insulating film is tight because of the sputtering technique. The resistance of the thin metal film resistive element is stable because of nitrogen atoms strongly bonded to tungsten atoms and silicon atoms.
摘要翻译：一种方法包括以下步骤：在安装在GaAs衬底上的SiN层绝缘膜上沉积Ti-Pt金属膜，蚀刻Ti-Pt金属膜以形成第一金属层，沉积SrTiO3绝缘膜，蚀刻SrTiO3绝缘膜形成绝缘膜，通过溅射法沉积WSiN金属膜，同时控制含氮气体的沉积压力，蚀刻WSiN金属膜，同时在绝缘膜上形成第二金属层，并在其上形成薄金属膜电阻元件 SiN层绝缘膜，沉积SiO 2钝化膜和制作通孔。 SrTiO3具有较高的相对介电常数，WSiN具有高熔点。 WSiN中的氮原子防止绝缘膜中的氧原子扩散到第二金属层。由于溅射技术，第二金属膜对绝缘膜的粘附是紧密的。由于氮原子与钨原子和硅原子牢固结合，薄金属薄膜电阻元件的电阻是稳定的。

8. 发明授权

US06352889B1 Method for fabricating capacitor and method for fabricating semiconductor device 有权
标题翻译：制造电容器的方法和制造半导体器件的方法
公开(公告)号：US06352889B1
公开(公告)日：2002-03-05
申请号：US09225560
申请日：1999-01-05
申请人： Mitsuru Nishitsuji
发明人： Mitsuru Nishitsuji
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L21/31691
摘要： A method for fabricating a capacitor according to the present invention includes the steps of: forming a lower-level electrode layer over a structure having thermally deteriorative properties; depositing an insulating film, containing a titanium oxide, on the lower-level electrode layer at a deposition temperature of 400° C. or less; conducting a heat treatment at a temperature higher than the deposition temperature and lower than 500° C. after the insulating film has been deposited; and depositing an upper-level electrode layer on the insulating film after the heat treatment has been conducted.
摘要翻译：根据本发明的制造电容器的方法包括以下步骤：在具有热劣化特性的结构上形成下层电极层; 在400℃或更低的沉积温度下在下层电极层上沉积含有氧化钛的绝缘膜; 在绝缘膜沉积之后，在高于沉积温度的温度下进行热处理并低于500℃; 并且在进行热处理之后在绝缘膜上沉积上层电极层。

9. 发明授权

US06329227B2 Method of patterning organic polymer film and method for fabricating semiconductor device 有权
公开(公告)号：US06329227B2
公开(公告)日：2001-12-11
申请号：US09789738
申请日：2001-02-22
申请人： Yoshiharu Anda , Mitsuru Nishitsuji , Katsuhiko Kawashima , Tsuyoshi Tanaka
发明人： Yoshiharu Anda , Mitsuru Nishitsuji , Katsuhiko Kawashima , Tsuyoshi Tanaka
IPC分类号： H01L2100
CPC分类号： H01L21/02118 , H01L21/0212 , H01L21/02274 , H01L21/28581 , H01L21/28587 , H01L21/3081 , H01L21/3088 , H01L21/31138 , H01L21/312
摘要： An organic polymer film patterning method includes the steps of: defining a resist film on a selected area of a substrate; depositing an organic polymer film over the substrate by a plasma CVD process so that the resist film is covered with part of the organic polymer film; and removing the resist film along with the part of the organic polymer film that has covered the resist film.

10. 发明授权

US5942772A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5942772A
公开(公告)日：1999-08-24
申请号：US44845
申请日：1998-03-20
申请人： Katsunori Nishii , Mitsuru Nishitsuji , Takahiro Yokoyama , Akiyoshi Tamura
发明人： Katsunori Nishii , Mitsuru Nishitsuji , Takahiro Yokoyama , Akiyoshi Tamura
IPC分类号： H01L29/812 , H01L21/335 , H01L21/338 , H01L21/76 , H01L29/10 , H01L29/778 , H01L29/80 , H01L31/0328 , H01L31/0336 , H01L31/109 , H01L31/074
CPC分类号： H01L29/66446 , H01L21/7605 , H01L29/1029 , H01L29/7783 , H01L29/802
摘要： A heterojunction epitaxial layer, including a first semiconductor layer containing Al and having a thickness of 50 nm or less and a second semiconductor layer different in composition from the first semiconductor layer, is formed on a substrate composed of semi-insulating GaAs. A gate electrode is formed on a specified region of the top surface of the heterojunction epitaxial layer. The source/drain formation regions of the heterojunction epitaxial layer are provided with respective high-concentration N-type impurity diffusion regions, on which respective ohmic electrodes are formed.
摘要翻译：在由半绝缘GaAs构成的衬底上形成异质结外延层，其包含含有Al且厚度为50nm以下的第一半导体层和与第一半导体层的组成不同的第二半导体层。栅电极形成在异质结外延层的顶表面的特定区域上。异质结外延层的源极/漏极形成区域设置有各自形成有各自的欧姆电极的高浓度N型杂质扩散区域。

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