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1. 发明授权

US4790632A Liquid crystal device having the microlenses in correspondence with the pixel electrodes 失效
标题翻译：具有与像素电极对应的微透镜的液晶装置
公开(公告)号：US4790632A
公开(公告)日：1988-12-13
申请号：US084232
申请日：1987-08-11
申请人： Tadashi Miyakawa , Kazuhiko Yanagihara , Hisao Oishi , Tsunehiko Takahashi , Takeshi Nakamura , Kazuhiko Akimoto , Mitsuaki Shioji
发明人： Tadashi Miyakawa , Kazuhiko Yanagihara , Hisao Oishi , Tsunehiko Takahashi , Takeshi Nakamura , Kazuhiko Akimoto , Mitsuaki Shioji
IPC分类号： B41J2/445 , G02F1/1335 , G02F1/13357 , G03F7/20 , G02F1/13
CPC分类号： G03F7/70275 , G02F1/133526 , G03F7/70241 , G03F7/70291
摘要： For recording an image on a photosensitive material with the employment of a liquid crystal device, the device used therein is conventionally constructed so as to modulate an amount of light rays transmitted therethrough or reflected thereby commonly by the control of an amount of electric voltage impressed to the liquid crystal device and/or impression timing or frequencies thereof. In this instance, although the light rays irradiated are considered normally as parallel, they are not intact strictly parallel light rays, and consequently unless the light rays transmitted from the device are converged by Selfoc lens arrays and the like, sufficient resolution can hardly be obtained on the photosensitive material on account of the light rays still having comparatively large diffusion coefficients. Since the liquid crystal device made in accordance with this invention is provided with its own image formation abilities, contact exposure with the photosensitive material is possible, and image formation optical systems which have been used in conjunction with the device is safely and advantageously eliminated, whereby parallelism limitations imposed on the irradiated rays can be reduced, and optical mechanisms therefor could be compact and have remarkably improved efficiencies.
摘要翻译：为了在使用液晶装置的感光材料上记录图像，其中使用的装置通常被构造成调制通过其传播或反射的光线的量，通过控制被施加到液晶装置和/或印象定时或其频率。在这种情况下，虽然照射的光线通常被认为是平行的，但它们并不完全是严格平行的光线，因此，除非从透镜阵列等收敛从器件透射的光线，否则几乎不能获得足够的分辨率由于仍然具有较大扩散系数的光线，在感光材料上。由于根据本发明制造的液晶装置具有其自身的图像形成能力，因此与感光材料的接触曝光是可能的，并且已经与装置结合使用的图像形成光学系统被安全和有利地消除，由此可以减少对照射的射线施加的平行度限制，并且其光学机制可以是紧凑的并且具有显着提高的效率。

2. 发明授权

US4836652A Liquid crystal shutter array having microlenses corresponding to the pixel electrodes 失效
标题翻译：具有对应于像素电极的微透镜的液晶快门阵列
公开(公告)号：US4836652A
公开(公告)日：1989-06-06
申请号：US120450
申请日：1987-11-13
申请人： Hisao Oishi , Kazuhiko Yanagihara , Tadashi Miyakawa , Takeshi Nakamura , Kazuhiko Akimoto , Mitsuaki Shioji
发明人： Hisao Oishi , Kazuhiko Yanagihara , Tadashi Miyakawa , Takeshi Nakamura , Kazuhiko Akimoto , Mitsuaki Shioji
IPC分类号： B41J2/465 , G02F1/1335 , G02F1/13357
CPC分类号： B41J2/465 , G02F1/133526
摘要： A liquid crystal shutter array requiring no separate focusing lens system. Microlenses for focusing the light incident upon a matrix of pixel electrodes are formed in a transparent substrate of the shutter assembly. A refractive index of light of each of the microlenses is set in a manner such that the incident angle .theta. of the light incident on the liquid crystal of the shutter through the microlenses satisfies; ##EQU1## where P, a, and d respectively represent the size of each of the photomasks, the length of a portion wherein each of the photomasks and corresponding ones of the pixel electrodes overlap, and the thickness of the transparent substrate on the light output side.
摘要翻译：不需要单独的聚焦透镜系统的液晶快门阵列。用于将入射到像素电极矩阵上的光聚焦的微透镜形成在快门组件的透明基板中。每个微透镜的光的折射率被设定为使得通过微透镜入射到快门的液晶上的光的入射角θ满足; 其中P，a和d分别表示每个光掩模的尺寸，其中每个光掩模和对应的像素电极重叠的部分的长度以及光输出上的透明基板的厚度侧。

3. 发明授权

US4842379A Image recording apparatus utilizing an ECB mode liquid crystal 失效
标题翻译：利用ECB模式液晶的图像记录装置
公开(公告)号：US4842379A
公开(公告)日：1989-06-27
申请号：US120451
申请日：1987-11-13
申请人： Hisao Oishi , Kazuhiko Yanagihara , Tadashi Miyakawa , Takeshi Nakamura , Kazuhiko Akimoto , Mitsuaki Shioji
发明人： Hisao Oishi , Kazuhiko Yanagihara , Tadashi Miyakawa , Takeshi Nakamura , Kazuhiko Akimoto , Mitsuaki Shioji
IPC分类号： B41J2/465 , G02F1/1347 , G02F1/139 , G06K15/12
CPC分类号： G06K15/1252 , B41J2/465 , G02F1/13473 , G02F1/1393
摘要： A color image recording apparatus employing a liquid crystal shutter array in which a color picture can be recorded with high quality using a small-sized apparatus and without requiring complex operations. A liquid crystal shutter array of the apparatus includes pixel electrodes and a shutter common electrode disposed in opposition to the pixel electrodes with a gap therebetween filled with a liquid crystal, a pair of transparent substrates supporting the pixel electrodes and the shutter common electrode by sandwiching the pixel electrodes and the shutter common electrode therebetween, and polarization plates stacked on the respective outsides of the transparent plates. A color liquid crystal layer is stacked on the liquid crystal shutter array constituted by first and second common electrodes disposed in opposition to each other with the gap therebetween filled with an ECB mode liquid crystal, and a pair of transparent substrates supporting the common electrodes.
摘要翻译：采用液晶快门阵列的彩色图像记录装置，其中可以使用小尺寸装置以高质量记录彩色图像，而不需要复杂的操作。装置的液晶快门阵列包括像素电极和与像素电极相对设置的与其间填充有液晶的间隙的快门公共电极，一对支撑像素电极的透明基板和快门公共电极，像素电极和其间的快门公共电极，以及堆叠在透明板的相应外侧上的偏振片。彩色液晶层层叠在由彼此相对配置的第一和第二公共电极构成的液晶快门阵列上，其中间隙填充有ECB模式液晶，以及一对支撑公共电极的透明基板。

4. 发明授权

US08116112B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08116112B2
公开(公告)日：2012-02-14
申请号：US12553048
申请日：2009-09-02
申请人： Tadashi Miyakawa , Daisaburo Takashima
发明人： Tadashi Miyakawa , Daisaburo Takashima
IPC分类号： G11C5/06
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4097 , G11C11/4099 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory apparatus includes: a bit line; a word line; a local bit line; a first switch unit provided between the local bit line and the bit; a memory cell connected to the bit line and the word line; a memory cell array including the memory cell; a first sense circuit connected to the bit line and configured to amplify a signal read out from the memory cell; and a second sense circuit connected to the local bit lines and configured to amplify a signal amplified by the first sense circuit, wherein the first switch unit disconnects the local bit line from the bit line when the first sense circuit amplifies the signal, and connects the local bit line to the bit line when the second sense circuit amplifies the signal amplified by the first sense circuit.
摘要翻译：一种半导体存储装置，包括：位线; 字线一个局部位线; 设置在本地位线和位之间的第一开关单元; 连接到位线和字线的存储单元; 包括存储单元的存储单元阵列; 连接到所述位线并被配置为放大从所述存储单元读出的信号的第一感测电路; 以及连接到本地位线并被配置为放大由第一感测电路放大的信号的第二感测电路，其中当第一感测电路放大信号时，第一开关单元将位置线与位线断开连接，当第二感测电路放大由第一感测电路放大的信号时，到位线的局部位线。

5. 发明授权

US07257011B2 Semiconductor memory having twisted bit line architecture 失效
标题翻译：具有扭曲位线架构的半导体存储器
公开(公告)号：US07257011B2
公开(公告)日：2007-08-14
申请号：US11258922
申请日：2005-10-27
申请人： Tadashi Miyakawa , Daisaburo Takashima
发明人： Tadashi Miyakawa , Daisaburo Takashima
IPC分类号： G11C5/08 , G11C5/06
CPC分类号： G11C11/22
摘要： A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in the first column, a first block select transistor which is connected between the first or second bit line and one end of the first cell block, a second cell block which is disposed in the second column, and a second block select transistor which is connected between the second or first bit line and one end of the second cell block.
摘要翻译：根据本发明的示例的半导体存储器包括具有扭曲位线架构的第一和第二位线，其中第一和第二位线在第一和第二列中以恒定周期交替地扭曲;第一单元块，其设置在第一列中，第一块选择晶体管连接在第一或第二位线与第一单元块的一端之间，第二单元块设置在第二列中，第二块选择晶体管，连接在第二或第二位线与第二单元块的一端之间。

6. 发明授权

US5553026A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5553026A
公开(公告)日：1996-09-03
申请号：US364348
申请日：1994-12-27
申请人： Hiroto Nakai , Tadashi Miyakawa , Shigeru Matsuda
发明人： Hiroto Nakai , Tadashi Miyakawa , Shigeru Matsuda
IPC分类号： G11C16/06 , G11C16/02 , G11C16/16 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/34 , G11C7/00
CPC分类号： G11C29/34 , G11C16/16 , G11C29/26
摘要： The non-volatile memory device comprises a memory cell array, a block decoder, and a decode signal reading section. The memory cell array has a plurality of cell blocks. Each of the cell blocks is composed of a plurality of memory cells arranged roughly into a matrix pattern. Each memory cell has a floating gate to or from which electrons are injected or extracted to write or erase data. The block decoder receives a block address, and outputs a decode signal to select a cell block corresponding to the block address from the cell blocks. The memory cells of the selected block are erased simultaneously. When a control signal is inputted to the block decoder, the block decoder outputs the decode signal to select all the cell blocks for erasure of the memory cells of all the cell blocks simultaneously, irrespective of the block address. The decode signal reading section outputs the decode signal to the outside. The decode signal is applied to the cell blocks and in parallel to the decode signal reading section itself and further outputted to the outside therethrough. In the memory device, the block erase function can be checked at a short time and additionally the other functional blocks can be checked simply.
摘要翻译：非易失性存储器件包括存储单元阵列，块解码器和解码信号读取部分。存储单元阵列具有多个单元块。每个单元块由大致排列成矩阵图案的多个存储单元构成。每个存储单元都有一个浮动栅极，从其中注入或提取电子以写入或擦除数据。块解码器接收块地址，并且输出解码信号以从单元块中选择与块地址相对应的单元块。所选块的存储单元同时被擦除。当控制信号被输入到块解码器时，块解码器输出解码信号以选择用于擦除所有单元块的存储单元的所有单元块，而与块地址无关。解码信号读取部将解码信号输出到外部。解码信号被施加到单元块并且与解码信号读取部分本身并行地进一步输出到外部。在存储器件中，可以在短时间内检查块擦除功能，另外可以简单地检查其他功能块。

7. 发明授权

US5384742A Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US5384742A
公开(公告)日：1995-01-24
申请号：US30343
申请日：1993-03-25
申请人： Tadashi Miyakawa , Masamichi Asano
发明人： Tadashi Miyakawa , Masamichi Asano
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/16 , G11C16/10 , G11C16/12 , G11C16/3418
摘要： A memory cell array is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another block (non-selected block) to moderate stress between the floating gate and source/drain, thereby preventing write error and erase error. In the program operation, the source and drain of a memory cell in the non-selected block are equalized to moderate an electric field between the control gate and source/drain and not to flow a channel current, thereby preventing write error. In carrying out a negative voltage erase method, prior to setting the source line and word line of a cell in a non-selected block to an erase voltage, the source and word lines are equalized. The equalization operation is released after the erase operation, thereby preventing malfunction of a non-selected cell.
摘要翻译： PCT No.PCT / JP91 / 01272 Sec。 371日期1993年3月25日 102（e）1993年3月25日PCT 1991年9月25日PCT公布。出版物WO92 / 05560 日期：1992年4月2日。存储单元阵列被分成多个块。在更改块（选择块）的数据时，将调节电压施加到另一个块（未选择块）中的存储单元的源极或控制栅极，以缓和浮动栅极和源极/漏极之间的应力，从而防止写入错误和擦除错误。在编程操作中，未选择的块中的存储单元的源极和漏极被均衡以控制控制栅极和源极/漏极之间的电场，并且不流过沟道电流，从而防止写入错误。在执行负电压擦除方法时，在将未选块中的单元的源极线和字线设置为擦除电压之前，源极和字线被均衡。在擦除操作之后释放均衡操作，从而防止未选择的单元的故障。

8. 发明授权

US5274131A 2-chloropropionaldehyde trimer and production process thereof 失效
标题翻译： 2-氯丙醛三聚体及其制备方法
公开(公告)号：US5274131A
公开(公告)日：1993-12-28
申请号：US781101
申请日：1991-10-22
申请人： Takashi Wakasugi , Tadashi Miyakawa , Naka Tonouchi , Takashi Yamauchi , Makoto Ishizuka
发明人： Takashi Wakasugi , Tadashi Miyakawa , Naka Tonouchi , Takashi Yamauchi , Makoto Ishizuka
IPC分类号： C07C45/55 , C07C45/63 , C07D323/04 , C07D323/06
CPC分类号： C07D323/04 , C07C45/55 , C07C45/63
摘要： A novel compound, a 2-chloropropionaldehyde trimer and a process of producing a 2-chloropropionaldehyde trimer by adding concentrated sulfuric acid to an organic solvent containing 2-chloropropionaldehyde and stirring the mixture at a temperature of from -5.degree. C. to 15.degree. C. to carry out the reaction.

9. 发明授权

US5210048A Nonvolatile semiconductor memory device with offset transistor and method for manufacturing the same 失效
标题翻译：具有偏置晶体管的非易失性半导体存储器件及其制造方法
公开(公告)号：US5210048A
公开(公告)日：1993-05-11
申请号：US924521
申请日：1992-08-04
申请人： Atsushi Shoji , Masamichi Asano , Tadashi Miyakawa , Tadayuki Taura , Michiharu Inami
发明人： Atsushi Shoji , Masamichi Asano , Tadashi Miyakawa , Tadayuki Taura , Michiharu Inami
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0425
摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.
摘要翻译：在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。在基板的源极和漏极区域上形成第一绝缘膜。在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。在第二绝缘膜上形成浮栅。在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。第一绝缘膜和杂质区用作存储单元的元件隔离区。

10. 发明授权

US4845550A Method and apparatus for processing picture image signals 失效
标题翻译：用于处理图像信号的方法和装置
公开(公告)号：US4845550A
公开(公告)日：1989-07-04
申请号：US906694
申请日：1986-09-11
申请人： Hitoshi Urabe , Tadashi Miyakawa , Osamu Shimazaki , Hisashi Kudo , Hideaki Kimura
发明人： Hitoshi Urabe , Tadashi Miyakawa , Osamu Shimazaki , Hisashi Kudo , Hideaki Kimura
IPC分类号： G03F3/08 , H04N1/60
CPC分类号： H04N1/6077 , H04N1/6027 , H04N1/6075
摘要： A method and process for processing picture image signals detects color separation signals of a color original image and then respectively converts these color separation signals into digital color separation signals. These digital color separation signals are then multiplied by predetermined coefficients and the results of these multiplications are sequentially accumulated for equalizing the levels of the digital color separation signals at a grey point of the original image so as to thereby obtain digital color separation signals which are converted to equivalent neutral densities. Hue signals of yellow, green, cyan, blue, magenta, and red which divide a color space into six hues are obtained from the digital color separation signals which are converted to the equivalent neutral densities. The hue signals are multiplied by predetermined color correction coefficients and the results thereof accumulated for color correction signals on yellow, magenta, and cyan. The digital color separation signals which are converted to the equivalent neutral densities are added to the color correction signals so as to thereby obtain selective color correction signals for recording the original image.
摘要翻译：用于处理图像图像信号的方法和处理检测彩色原始图像的色彩分离信号，然后分别将这些分色信号转换为数字分色信号。然后将这些数字分色信号乘以预定系数，并且顺序地累积这些乘法的结果，以均衡原始图像的灰度点处的数字分色信号的电平，从而获得转换的数字色分离信号达到等效中性密度。从转换为等效中性密度的数字分色信号获得黄色，绿色，青色，蓝色，品红色和红色的色调信号，将色彩空间分为六种色调。色相信号乘以预定的颜色校正系数，并且其结果累积用于黄色，品红色和青色上的颜色校正信号。转换为等效中性密度的数字色分离信号被加到颜色校正信号中，从而获得用于记录原始图像的选择性色彩校正信号。

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