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1. 发明授权

US06348402B1 Method of manufacturing a copper interconnect 失效
标题翻译：制造铜互连的方法
公开(公告)号：US06348402B1
公开(公告)日：2002-02-19
申请号：US09526880
申请日：2000-03-16
申请人： Takashi Kawanoue , Tetsuo Matsuda , Hisashi Kaneko , Tadashi Iijima
发明人： Takashi Kawanoue , Tetsuo Matsuda , Hisashi Kaneko , Tadashi Iijima
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/76807 , H01L21/76831 , H01L21/76844 , H01L21/76855 , H01L21/76856 , H01L21/76888 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A groove or hole is formed in an insulating layer formed on a semiconductor substrate, and a first conductive layer including a first metal element is formed on a surface of the insulating layer. By oxidizing the first conductive layer, an oxide layer of the first metal element is formed on a surface of the first conductive layer. A second conductive layer including a second metal element having a free energy of oxide formation lower than that of the first metal element is deposited thereon. By reducing the oxide layer of the first metal element by the second metal element, an oxide layer of the second metal element is formed at the interface between the first conductive layer and the second conductive layer. Further, an interconnection is buried in the groove or hole of the insulating layer. Thereby, a thin second metal oxide layer having excellent barrier properties against an interconnection material and excellent adhesion to the interconnection material can be selectively formed with a uniform thickness on the surface of the first conductive layer used as a barrier metal layer of the interconnection.
摘要翻译：在形成于半导体衬底上的绝缘层中形成沟槽，在绝缘层的表面上形成包括第一金属元件的第一导电层。通过氧化第一导电层，在第一导电层的表面上形成第一金属元素的氧化物层。在其上沉积包括具有低于第一金属元素的自由能的氧化物形成的第二金属元素的第二导电层。通过由第二金属元件还原第一金属元件的氧化物层，在第一导电层和第二导电层之间的界面处形成第二金属元素的氧化物层。此外，互连被埋在绝缘层的凹槽或孔中。由此，可以在用作互连的阻挡金属层的第一导电层的表面上选择性地形成具有优良的互连材料阻隔性和对互连材料的优异粘附性的薄的第二金属氧化物层。

2. 发明授权

US06368951B2 Semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US06368951B2
公开(公告)日：2002-04-09
申请号：US09903992
申请日：2001-07-13
申请人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
IPC分类号： H01L214763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/76807 , H01L21/76814 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76849 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L2221/1026 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.
摘要翻译：一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层，在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。

3. 发明授权

US06291891B1 Semiconductor device manufacturing method and semiconductor device 有权
公开(公告)号：US06291891B1
公开(公告)日：2001-09-18
申请号：US09228642
申请日：1999-01-12
申请人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
IPC分类号： H01L2348
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/76807 , H01L21/76814 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76849 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L2221/1026 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

4. 发明授权

US6150270A Method for forming barrier layer for copper metallization 有权
标题翻译：用于形成铜金属化的阻挡层的方法
公开(公告)号：US6150270A
公开(公告)日：2000-11-21
申请号：US226722
申请日：1999-01-07
申请人： Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko
发明人： Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76855
摘要： A method comprises forming a barrier layer for copper metallization, selectively forming a silicon film on a surface of copper wiring formed on the main surface of a semiconductor substrate, and reacting the silicon film with a non-copper metal and/or nitrogen to form a barrier layer in a self-aligned manner relative to the copper wiring. In the method, the capacitance increase in the copper wirings formed is prevented, and the barrier layer formed has a satisfactory barrier property of protecting the copper wirings.
摘要翻译：一种方法包括形成用于铜金属化的阻挡层，在形成在半导体衬底的主表面上的铜布线的表面上选择性地形成硅膜，并使硅膜与非铜金属和/或氮反应形成阻挡层以相对于铜布线的自对准方式。在该方法中，防止形成的铜布线的电容增加，形成的阻挡层具有保护铜布线的令人满意的阻挡性。

5. 发明授权

US06750143B1 Method for forming a plating film, and device for forming the same 失效
标题翻译：镀膜的形成方法及其形成装置
公开(公告)号：US06750143B1
公开(公告)日：2004-06-15
申请号：US09370888
申请日：1999-08-10
申请人： Tadashi Iijima , Tetsuo Matsuda
发明人： Tadashi Iijima , Tetsuo Matsuda
IPC分类号： H01L2144
CPC分类号： H01L21/288 , C23C18/1632 , C23C18/1651 , C23C18/1893 , H01L21/76877
摘要： A desired plating film is formed on a surface of a substrate to be treated by performing a film-depositing step based on electroless plating and an etching step alternately and repeatedly. In the film-depositing step, an electroless plating solution is supplied from a nozzle to the surface of the substrate. In the etching step, an etching solution is supplied from a nozzle to the surface of the substrate.
摘要翻译：通过交替地重复地进行基于无电解电镀和蚀刻步骤的成膜步骤，在待处理的基板的表面上形成期望的镀膜。在成膜步骤中，将无电镀液从喷嘴供给到基板的表面。在蚀刻步骤中，将蚀刻溶液从喷嘴供给到基板的表面。

6. 发明申请

US20120112308A1 SEMICONDUCTOR DEVICE, SEMICONDUCTOR GROUP MEMBER AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 审中-公开
标题翻译：半导体器件，半导体器件组件和半导体器件制造方法
公开(公告)号：US20120112308A1
公开(公告)日：2012-05-10
申请号：US13238617
申请日：2011-09-21
申请人： Tetsuo Matsuda , Tomomi Imamura
发明人： Tetsuo Matsuda , Tomomi Imamura
IPC分类号： H01L25/00 , H01L21/66 , H01L21/78
CPC分类号： H01L29/7813 , H01L22/14 , H01L23/3107 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/072 , H01L29/41741 , H01L29/42372 , H01L29/42376 , H01L29/7811 , H01L2224/04034 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/06051 , H01L2224/0615 , H01L2224/371 , H01L2224/40245 , H01L2224/40499 , H01L2224/41113 , H01L2224/4117 , H01L2224/48247 , H01L2224/49113 , H01L2224/4917 , H01L2224/94 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2224/03 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： According to one embodiment, a semiconductor device includes a device portion, a first electrode portion, a second electrode portion and a protruding portion. The device portion is provided on a substrate. The first electrode portion is provided on the device portion and is electrically contacted with the device portion. The second electrode portion is provided on the device portion separated from the first electrode portion, and electrically contacted with the device portion. The protruding portion is provided on the device portion and protrudes outward from a peripheral portion of the first electrode portion and the second electrode portion.
摘要翻译：根据一个实施例，半导体器件包括器件部分，第一电极部分，第二电极部分和突出部分。器件部分设置在衬底上。第一电极部分设置在器件部分上并与器件部分电接触。第二电极部分设置在与第一电极部分分离的器件部分上，并与器件部分电接触。突出部分设置在装置部分上并从第一电极部分和第二电极部分的周边部分向外突出。

7. 发明授权

US07575664B2 Plating method 失效
标题翻译：电镀方法
公开(公告)号：US07575664B2
公开(公告)日：2009-08-18
申请号：US11135328
申请日：2005-05-24
申请人： Tetsuo Matsuda , Hisashi Kaneko , Katsuya Okumura
发明人： Tetsuo Matsuda , Hisashi Kaneko , Katsuya Okumura
IPC分类号： C25D21/12
CPC分类号： C25D5/16 , C25D5/02 , C25D5/06 , C25D7/123 , C25D17/001 , C25D17/12 , H01L21/2885 , H01L21/76877 , H05K3/423
摘要： A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.
摘要翻译：对形成在具有凹陷图案的基板上的导电层施加阴极电位。将与阳极电接触的电镀溶液供给到导电层，以在导电层上形成镀膜。此时，通过使包含电镀液的浸渍部件面对导电层而供给电镀液。由于电镀溶液滞留在凹陷中，所以与基板的上表面相比，供给电镀液的量较多，因此抑制了镀膜的镀覆速度。因此，可以在诸如凹槽或孔的凹陷中优先地形成镀膜。

8. 发明申请

US20080251385A1 PLATING APPARATUS 审中-公开
标题翻译：电镀设备
公开(公告)号：US20080251385A1
公开(公告)日：2008-10-16
申请号：US12116562
申请日：2008-05-07
申请人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
发明人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
IPC分类号： C25D21/12
CPC分类号： H01L21/6719 , C25D7/123 , C25D17/001 , C25D17/12 , C25D17/14 , H01L21/2885 , H01L21/67046 , H01L21/67051 , H01L21/6708 , H01L21/6715 , H01L21/6723 , H01L21/76877 , H01L21/76879 , H01L2924/0002 , H05K3/423 , H01L2924/00
摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
摘要翻译：用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。密封材料90接触表面的周缘部分，以水密的方式密封该部分。阴极电极88在与基板接触时通过电流。阴极部38与基板保持部36一体旋转。电极臂部分30在阴极部分38的上方并且可水平和垂直地移动，并且阳极98面向下。将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。因此，电镀处理和附带的处理可以通过单个单元进行。

9. 发明授权

US06998342B2 Electronic device manufacturing method 失效
公开(公告)号：US06998342B2
公开(公告)日：2006-02-14
申请号：US10835319
申请日：2004-04-30
申请人： Tetsuo Matsuda , Hiroshi Toyoda , Hisashi Kaneko
发明人： Tetsuo Matsuda , Hiroshi Toyoda , Hisashi Kaneko
IPC分类号： H01L21/44
CPC分类号： H01L21/76874 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/405 , C23C18/54 , C23C28/00 , C25D7/123 , H01L21/2855 , H01L21/288 , H01L21/76867 , H01L21/76868 , H01L21/76873 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.

10. 发明授权

US06632335B2 Plating apparatus 有权
标题翻译：电镀装置
公开(公告)号：US06632335B2
公开(公告)日：2003-10-14
申请号：US09742110
申请日：2000-12-22
申请人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
发明人： Junji Kunisawa , Mitsuko Odagaki , Natsuki Makino , Koji Mishima , Kenji Nakamura , Hiroaki Inoue , Norio Kimura , Tetsuo Matsuda , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura , Manabu Tsujimura , Toshiyuki Morita
IPC分类号： C25D2112
CPC分类号： H01L21/6719 , C25D7/123 , C25D17/001 , C25D17/12 , C25D17/14 , H01L21/2885 , H01L21/67046 , H01L21/67051 , H01L21/6708 , H01L21/6715 , H01L21/6723 , H01L21/76877 , H01L21/76879 , H01L2924/0002 , H05K3/423 , H01L2924/00
摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
摘要翻译：用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。该装置具有将待镀表面向上水平保持并旋转的衬底的衬底保持部分 36 。密封材料 90 接触表面的外围边缘部分，以水密的方式密封该部分。当与基板接触时，阴极电极 88 通过电流。阴极部分 38 与衬底保持部分 36 整体旋转。电极臂部分 30 在阴极部分 38 之上，水平和垂直移动并具有阳极 PDAT> 98 面朝下。将电镀液倒入要被镀表面和靠近待镀表面的阳极 98 之间的空间中。因此，电镀处理和附带的处理可以通过单个单元执行

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