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1. 发明授权

US08648393B2 Transistor and semiconductor device 有权
标题翻译：晶体管和半导体器件
公开(公告)号：US08648393B2
公开(公告)日：2014-02-11
申请号：US13372159
申请日：2012-02-13
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号： H01L27/148
CPC分类号： H01L27/1203 , H01L21/28202 , H01L29/518 , H01L29/78654 , H01L29/78696
摘要： An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm−3 to achieve a large gate voltage swing.
摘要翻译：累积模式晶体管的沟道区域中的半导体层的杂质浓度高于2×1017cm-3，以实现大的栅极电压摆动。

2. 发明授权

US08138527B2 Transistor and semiconductor device 有权
标题翻译：晶体管和半导体器件
公开(公告)号：US08138527B2
公开(公告)日：2012-03-20
申请号：US12309244
申请日：2007-07-12
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号： H01L27/148
CPC分类号： H01L27/1203 , H01L21/28202 , H01L29/518 , H01L29/78654 , H01L29/78696
摘要： An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm−3 to achieve a large gate voltage swing.
摘要翻译：累积模式晶体管的沟道区域中的半导体层的杂质浓度高于2×1017cm-3，以实现大的栅极电压摆动。

3. 发明授权

US08492879B2 Semiconductor substrate and semiconductor device 有权
标题翻译：半导体衬底和半导体器件
公开(公告)号：US08492879B2
公开(公告)日：2013-07-23
申请号：US12681576
申请日：2008-10-06
申请人： Tadahiro Ohmi , Akinobu Teramoto , Tomoyuki Suwa , Rihito Kuroda , Hideo Kudo , Yoshinori Hayamizu
发明人： Tadahiro Ohmi , Akinobu Teramoto , Tomoyuki Suwa , Rihito Kuroda , Hideo Kudo , Yoshinori Hayamizu
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/02433 , H01L29/78
摘要： On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction).
摘要翻译：在半导体基板的表面上，以大致相同的方向形成有以原子台阶逐步形成的多个台阶。使用半导体衬底，形成MOS晶体管，使得在载流子行进方向（源 - 漏方向）上不存在台阶。

4. 发明授权

US08362567B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08362567B2
公开(公告)日：2013-01-29
申请号：US12309245
申请日：2007-07-12
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号： H01L21/70
CPC分类号： H01L29/045 , H01L21/02057 , H01L21/28194 , H01L21/28202 , H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/456 , H01L29/518 , H01L29/785 , H01L2029/7857
摘要： In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10−11 Ωcm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.
摘要翻译：在半导体装置中，以峰 - 谷（PV）值为单位，平坦度为0.3nm以下的程度是通过在加有荧光的状态下加氢的超纯水冲洗硅表面而实现的通过在电极和硅之间设定0.2eV以下的功函数差来实现10-11＆OHgr·cm 2以下的接触电阻。因此，半导体器件可以在10GHz或更高的频率上工作。

5. 发明申请

US20120146102A1 TRANSISTOR AND SEMICONDUCTOR DEVICE 有权
标题翻译：晶体管和半导体器件
公开(公告)号：US20120146102A1
公开(公告)日：2012-06-14
申请号：US13372159
申请日：2012-02-13
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号： H01L29/04 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/28202 , H01L29/518 , H01L29/78654 , H01L29/78696
摘要： An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm−3 to achieve a large gate voltage swing.
摘要翻译：累积模式晶体管的沟道区域中的半导体层的杂质浓度高于2×1017cm-3，以实现大的栅极电压摆动。

6. 发明申请

US20100059830A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100059830A1
公开(公告)日：2010-03-11
申请号：US12309245
申请日：2007-07-12
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号： H01L29/417 , H01L27/092
CPC分类号： H01L29/045 , H01L21/02057 , H01L21/28194 , H01L21/28202 , H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/456 , H01L29/518 , H01L29/785 , H01L2029/7857
摘要： In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10−11 Ωcm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.
摘要翻译：在半导体装置中，以峰 - 谷（PV）值为单位，平坦度为0.3nm以下的程度是通过在加有荧光的状态下加氢的超纯水冲洗硅表面而实现的通过在电极和硅之间设定0.2eV以下的功函数差来实现10-11＆OHgr·cm 2以下的接触电阻。因此，半导体器件可以在10GHz或更高的频率上工作。

7. 发明申请

US20110042725A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110042725A1
公开(公告)日：2011-02-24
申请号：US12989713
申请日：2009-04-10
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号： H01L27/092 , H01L29/06 , H01L29/78
CPC分类号： H01L27/1203 , H01L27/0883 , H01L27/092 , H01L29/045 , H01L29/458 , H01L29/78654 , H01L29/78696
摘要： With inversion-mode transistors, intrinsic-mode transistors, or semiconductor-layer accumulation-layer current controlled accumulation-mode transistors, variation in threshold voltages becomes large in miniaturized generations due to statistical variation in impurity atom concentrations and thus it is difficult to maintain the reliability of an LSI. Provided is a bulk current controlled accumulation-mode transistor which is formed by controlling the thickness and the impurity atom concentration of a semiconductor layer so that the thickness of a depletion layer becomes greater than that of the semiconductor layer. For example, by setting the thickness of the semiconductor layer to 100 nm and setting the impurity concentration thereof to be higher than 2×1017 [cm−3], the standard deviation of variation in threshold values can be made smaller than a power supply voltage-based allowable variation value.
摘要翻译：利用反型晶体管，固有模式晶体管或半导体层累积层电流控制的累积模式晶体管，由于杂质原子浓度的统计变化，小型化电路中阈值电压的变化变大，因此难以维持 LSI的可靠性。提供了通过控制半导体层的厚度和杂质原子浓度使得耗尽层的厚度变得大于半导体层的厚度而形成的体电流控制堆积模式晶体管。例如，通过将半导体层的厚度设定为100nm，将其杂质浓度设定为高于2×1017 [cm-3]，可以使阈值的变化的标准偏差小于电源电压的允许变化值。

8. 发明申请

US20100213516A1 SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体衬底和半导体器件
公开(公告)号：US20100213516A1
公开(公告)日：2010-08-26
申请号：US12681576
申请日：2008-10-06
申请人： Tadahiro Ohmi , Akinobu Teramoto , Tomoyuki Suwa , Rihito Kuroda , Hideo Kudo , Yoshinori Hayamizu
发明人： Tadahiro Ohmi , Akinobu Teramoto , Tomoyuki Suwa , Rihito Kuroda , Hideo Kudo , Yoshinori Hayamizu
IPC分类号： H01L29/04 , H01L29/786
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/02433 , H01L29/78
摘要： On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction).
摘要翻译：在半导体基板的表面上，以大致相同的方向形成有以原子台阶逐步形成的多个台阶。使用半导体衬底，形成MOS晶体管，使得在载流子行进方向（源 - 漏方向）上不存在台阶。

9. 发明申请

US20090309138A1 Transistor and semiconductor device 有权
标题翻译：晶体管和半导体器件
公开(公告)号：US20090309138A1
公开(公告)日：2009-12-17
申请号：US12309244
申请日：2007-07-12
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号： H01L29/786 , H01L29/04
CPC分类号： H01L27/1203 , H01L21/28202 , H01L29/518 , H01L29/78654 , H01L29/78696
摘要： An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm−3 to achieve a large gate voltage swing.
摘要翻译：累积模式晶体管的沟道区中的半导体层的杂质浓度高于2×10 17 cm -3，以实现大的栅极电压摆动。

10. 发明申请

US20140306344A1 WIRING STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING WIRING STRUCTURE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：布线结构，包括布线结构的半导体器件，以及制造半导体器件的方法
公开(公告)号：US20140306344A1
公开(公告)日：2014-10-16
申请号：US14313026
申请日：2014-06-24
申请人： Shigetoshi Sugawa , Akinobu Teramoto , Rihito Kuroda , Gu Xun
发明人： Shigetoshi Sugawa , Akinobu Teramoto , Rihito Kuroda , Gu Xun
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/02063 , H01L21/0212 , H01L21/02126 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76807 , H01L21/76808 , H01L21/76831 , H01L21/76843 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： There is provided with a wiring structure. The wiring stracture has a damascene wiring structure including a metal wiring. The metal wiring is provided in direct contact with an upper surface of a barrier film (SiC(O, N) film) containing silicon (Si), carbon (C), and at least one of oxygen (O) and nitrogen (N) as constituent components.
摘要翻译：设有布线结构。布线结构具有包括金属布线的镶嵌布线结构。金属布线与含有硅（Si），碳（C）和氧（O）和氮（N）中的至少一种的阻挡膜（SiC（O，N）膜）的上表面直接接触，作为组成部分。

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