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1. 发明申请

US20070289772A1 Electronic Circuit 有权
标题翻译：电子电路
公开(公告)号：US20070289772A1
公开(公告)日：2007-12-20
申请号：US10588769
申请日：2005-02-14
申请人： Tadahiro Kuroda , Daisuke Mizoguchi , Yusmeeraz Yusof , Noriyuki Miura , Takayasu Sakurai
发明人： Tadahiro Kuroda , Daisuke Mizoguchi , Yusmeeraz Yusof , Noriyuki Miura , Takayasu Sakurai
IPC分类号： H01S4/00 , H05K1/16
CPC分类号： H05K1/165 , H01F17/0006 , H01F2038/143 , H01L25/0657 , H01L2224/32145 , H01L2225/06527 , H05K1/0237 , H05K1/0239 , Y10T29/49002
摘要： The present invention has an object to provide an electronic circuit capable of efficiently transmitting signals in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. In the present invention, LSI chips are stacked in three layers, and a bus is formed over three chips. The first through the third transmitter coils 13a, 13b, 13c and the first through the third receiver coils 15a, 15b, 15c are formed by wiring on the first through the third LSI chips 11a, 11b, 11c. These three pairs of transmitter and receiver coils are disposed so that the centers of the openings thereof are coincident with each other, whereby three pairs of transmitter and receiver coils 13 and 15 form inductive coupling to enable communications. The first through the third transmitter circuits 12a, 12b, 12c are connected to the first through the third transmitter coils 13a, 13b and 13c, respectively, and the first through the third receiver circuits 14a, 14b, 14c are connected to the first through the third receiver coils 15a, 15b, 15c, respectively.
摘要翻译：本发明的目的是提供一种能够在三维或三维以上的基板上传输信号的情况下，有效地发送信号的电子电路。在本发明中，将LSI芯片堆叠成三层，在三块芯片上形成总线。通过在第一至第三LSI芯片11a，11b，11上的布线形成第一至第三发送线圈13a，13b，13c和第一至第三接收线圈15a，15b，15c， C。这三对发射器和接收器线圈被布置成使得其开口的中心彼此重合，由此三对发射器和接收器线圈13和15形成感应耦合以实现通信。第一至第三发送器电路12a，12b，12c分别连接到第一至第三发送器线圈13a，13b和13c，并且第一至第三接收器电路14a， 14c分别连接到第一至第三接收线圈15a，15b，15c。

2. 发明授权

US07768790B2 Electronic circuit 有权
标题翻译：电子电路
公开(公告)号：US07768790B2
公开(公告)日：2010-08-03
申请号：US10588769
申请日：2005-02-14
申请人： Tadahiro Kuroda , Daisuke Mizoguchi , Yusmeeraz Binti Yusof , Noriyuki Miura , Takayasu Sakurai
发明人： Tadahiro Kuroda , Daisuke Mizoguchi , Yusmeeraz Binti Yusof , Noriyuki Miura , Takayasu Sakurai
IPC分类号： H05K7/00
CPC分类号： H05K1/165 , H01F17/0006 , H01F2038/143 , H01L25/0657 , H01L2224/32145 , H01L2225/06527 , H05K1/0237 , H05K1/0239 , Y10T29/49002
摘要： An electronic circuit capable of efficiently transmitting signals in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. In the present invention, LSI chips are stacked in three layers, and a bus is formed over three chips. The first through the third transmitter coils 13a, 13b, 13c and the first through the third receiver coils 15a, 15b, 15c are formed by wiring on the first through the third LSI chips 11a, 11b, 11c. These three pairs of transmitter and receiver coils are disposed so that the centers of the openings thereof are coincident with each other, whereby three pairs of transmitter and receiver coils 13 and 15 form inductive coupling to enable communications. The first through the third transmitter circuits 12a, 12b, 12c are connected to the first through the third transmitter coils 13a, 13b and 13c, respectively, and the first through the third receiver circuits 14a, 14b, 14c are connected to the first through the third receiver coils 15a, 15b, 15c, respectively.
摘要翻译：在三维或三维以上的基板上传输信号的情况下能够高效地发送信号的电子电路。在本发明中，将LSI芯片堆叠成三层，在三块芯片上形成总线。通过第一至第三LSI芯片11a，11b，11c上的布线形成第一至第三发送线圈13a，13b，13c和第一至第三接收线圈15a，15b，15c。这三对发射器和接收器线圈被布置成使得其开口的中心彼此重合，由此三对发射器和接收器线圈13和15形成感应耦合以实现通信。第一至第三发送器电路12a，12b，12c分别连接到第一至第三发送器线圈13a，13b和13c，并且第一至第三接收器电路14a，14b，14c连接到第一至第第三接收线圈15a，15b，15c。

3. 发明授权

US5933029A Semiconductor integrated circuit device comprising a bias circuit, a driver circuit, and a receiver circuit 失效
标题翻译：半导体集成电路器件包括偏置电路，驱动电路和接收器电路
公开(公告)号：US5933029A
公开(公告)日：1999-08-03
申请号：US848126
申请日：1997-04-28
申请人： Tadahiro Kuroda , Takayasu Sakurai
发明人： Tadahiro Kuroda , Takayasu Sakurai
IPC分类号： H03K19/0175 , G06F12/00 , G06F13/16 , H01L27/02 , H03K19/003 , H03K19/0185 , H03K19/096 , H04L25/02 , G05F3/02 , H03K19/094
CPC分类号： H01L27/0218 , H03K19/00384 , H03K19/018507 , H01L2224/05554 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/13091 , H01L2924/3011 , H01L2924/30111
摘要： To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage; a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit and the first supply voltage, and for driving a transfer path by the converted signal; a voltage divider circuit for dividing an output voltage of the bias circuit; and a receiver circuit for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first/supply voltage and the second supply voltage.
摘要翻译：为了最小化功率消耗，所公开的半导体集成电路器件包括：用于产生固定在第一电源电压和第二电源电压之间的预定电压的偏置电路; 用于接收每个在第一和第二电源电压之间振动的反相输入信号和非反相输入信号的驱动器电路，用于将接收到的输入信号转换成在偏置电路的输出电压和第一电源电压之间振动的信号，并且用于通过转换的信号驱动传送路径; 用于分压偏置电路的输出电压的分压电路; 以及接收器电路，用于通过使用分压器电路的输出作为参考电压来检测用于驱动传输路径的信号，并且用于将检测到的信号转换为在第一/电源电压和第二电源电压之间振动的信号。

4. 发明授权

US06215159B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06215159B1
公开(公告)日：2001-04-10
申请号：US09046980
申请日：1998-03-24
申请人： Tetsuya Fujita , Gensoh Matsubara , Tadahiro Kuroda , Takayasu Sakurai
发明人： Tetsuya Fujita , Gensoh Matsubara , Tadahiro Kuroda , Takayasu Sakurai
IPC分类号： H01L2976
CPC分类号： H03K19/0016 , G05F3/242
摘要： CMOS logic circuit CM is of a structure in which the threshold value of constituent transistors MP1, MN1, etc. thereof is set to value lower than ordinary value, and the threshold value of a stand-by state current control P-channel MOS transistor MP2 is set to value higher than the threshold value of the transistors MP1, MN1, etc. constituting the CMOS logic circuit CM. A level conversion circuit 10 outputs a signal in which low level indicates negative voltage and high level indicates the same potential VDD as that of the first power supply line P1 in dependency upon high level and low level of signal applied to control input terminal SIG to thereby carry out ON/OFF control of the P-channel MOS transistor MP2. Accordingly, lower voltage of 0V or less, or higher voltage of VDD or more is applied to the gate of the stand-by state current control MOS transistor in the CMOS logic circuit, whereby even if the power supply voltage VDD is caused to be low voltage, ON/OFF operation of the stand-by state current control MOS transistor is securely carried out.
摘要翻译： CMOS逻辑电路CM具有将其构成晶体管MP1，MN1等的阈值设定为低于普通值的值的结构，并且待机状态电流控制P沟道MOS晶体管MP2的阈值被设定为高于构成CMOS逻辑电路CM的晶体管MP1，MN1等的阈值的值。电平转换电路10根据施加到控制输入端子SIG的高电平和低电平信号，输出低电平指示负电压的信号，高电平表示与第一电源线P1相同的电位VDD，由此进行P沟道MOS晶体管MP2的ON / OFF控制。因此，在CMOS逻辑电路中的待机状态电流控制MOS晶体管的栅极上施加0V以下的较低电压或VDD以上的较高电压，由此即使电源电压VDD变低备用电流控制MOS晶体管的电压，ON / OFF操作被可靠地执行。

5. 发明授权

US6037805A Integrated circuit device having small amplitude signal transmission 有权
标题翻译：具有小振幅信号传输的集成电路装置
公开(公告)号：US6037805A
公开(公告)日：2000-03-14
申请号：US280726
申请日：1999-03-29
申请人： Tadahiro Kuroda , Takayasu Sakurai
发明人： Tadahiro Kuroda , Takayasu Sakurai
IPC分类号： H03K19/0175 , G06F12/00 , G06F13/16 , H01L27/02 , H03K19/003 , H03K19/0185 , H03K19/096 , H04L25/02 , H01L25/00 , H03K19/00 , H03K19/094
CPC分类号： H01L27/0218 , H03K19/00384 , H03K19/018507 , H01L2224/05554 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/13091 , H01L2924/3011 , H01L2924/30111
摘要： To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage; a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit and the first supply voltage, and for driving a transfer path by the converted signal; a voltage divider circuit for dividing an output voltage of the bias circuit; and a receiver circuit for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first supply voltage and the second supply voltage.
摘要翻译：为了最小化功率消耗，所公开的半导体集成电路器件包括：用于产生固定在第一电源电压和第二电源电压之间的预定电压的偏置电路; 用于接收每个在第一和第二电源电压之间振动的反相输入信号和非反相输入信号的驱动器电路，用于将接收到的输入信号转换成在偏置电路的输出电压和第一电源电压之间振动的信号，并且用于通过转换的信号驱动传送路径; 用于分压偏置电路的输出电压的分压电路; 以及接收器电路，用于通过使用分压器电路的输出作为参考电压来检测用于驱动传输路径的信号，并且用于将检测到的信号转换为在第一电源电压和第二电源电压之间振动的信号。

6. 发明授权

US08618870B2 Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit 失效
标题翻译：锁存电路的电压特性调节方法，半导体器件的电压特性调节方法和锁存电路的电压特性调节器
公开(公告)号：US08618870B2
公开(公告)日：2013-12-31
申请号：US13377009
申请日：2010-06-11
申请人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
发明人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
IPC分类号： G05F1/10
CPC分类号： G11C11/413
摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.
摘要翻译：电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对导通晶体管的栅极与半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善。

7. 发明申请

US20060039182A1 Self-aligned row-by-row dynamic VDD SRAM 失效
标题翻译：自对准逐行动态VDD SRAM
公开(公告)号：US20060039182A1
公开(公告)日：2006-02-23
申请号：US11205466
申请日：2005-08-16
申请人： Takayasu Sakurai , Hiroshi Kawaguchi , Robert Fayez
发明人： Takayasu Sakurai , Hiroshi Kawaguchi , Robert Fayez
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.
摘要翻译：存储单元阵列包括以矩阵形式布置的多个存储单元。字线和电源线分别连接到布置在每一行中的多个存储单元。电源线/字线控制电路连接到每个字线和每个电源线。在逐行访问多个存储单元时，控制电路提高电源线的电压，并且在所有位置的电源线的电压达到高电压之后，开始字线的激活。另一方面，在从访问状态转到非访问状态时，控制电路使字线停止，并且在字线的电压在所有位置变化为接地电压之后，改变电源的电压供电线路为低电压。

8. 发明授权

US5434517A ECL output buffer with a MOS transistor used for tristate enable 失效
标题翻译：具有用于三态使能的MOS晶体管的ECL输出缓冲器
公开(公告)号：US5434517A
公开(公告)日：1995-07-18
申请号：US215174
申请日：1994-03-21
申请人： Hiroyuki Hara , Takayasu Sakurai
发明人： Hiroyuki Hara , Takayasu Sakurai
IPC分类号： H03K19/08 , H03K19/018 , H03K19/082 , H03K19/086
CPC分类号： H03K19/01812 , H03K19/0826
摘要： An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.
摘要翻译： ECL输出缓冲电路由输出缓冲电路主要部分及其控制电路构成。在输出缓冲电路主要部分中，差分开关的输出被输入到双极晶体管（射极跟随器）的基极。双极晶体管的发射极连接到输出端子。接地电位施加到双极晶体管的集电极。 MOS晶体管的沟道导电路径的一端连接到双极晶体管的基极。通道导电路径的另一端经由恒流源与电源端子连接。控制电路控制MOS晶体管的ON / OFF操作和双极晶体管的输出电平。当输出缓冲器电路主要部分被设置在待机状态时，控制电路进行控制以将MOS晶体管设置在导通状态，并将双极晶体管的输出设置为低电平。

9. 发明授权

US4958326A Semiconductor memory device having a function of simultaneously clearing part of memory data 失效
标题翻译：具有同时清除部分存储器数据的功能的半导体存储器件
公开(公告)号：US4958326A
公开(公告)日：1990-09-18
申请号：US274555
申请日：1988-11-22
申请人： Takayasu Sakurai
发明人： Takayasu Sakurai
IPC分类号： G11C11/401 , G11C7/20 , G11C8/12
CPC分类号： G11C7/20 , G11C8/12
摘要： A semiconductor memory device includes a first memory cell array and a second memory cell array section into which the same data can be simultaneously written. Logic gates are provided between the word lines of the first memory cell array section and the respective word lines of the second memory cell array section. In the normal operation mode, the logic gates connect each of the rows of memory cells in the first memory cell array section to a corresponding one of the rows of memory cells in the second memory cell array section, and set each of the rows of memory cells in the second memory cell array section to a selected level when the same data is simultaneously written into the memory cells of the second memory cell array section. When each of the rows of memory cells in the second memory cell array section is set to the selected level, all the columns of the memory cells in the second memory cell array section are simultaneously selected and the same data is simultaneously written into the second memory cell array section.

10. 发明授权

US4905192A Semiconductor memory cell 失效
标题翻译：半导体存储单元
公开(公告)号：US4905192A
公开(公告)日：1990-02-27
申请号：US175252
申请日：1988-03-30
申请人： Kazutaka Nogami , Takayasu Sakurai
发明人： Kazutaka Nogami , Takayasu Sakurai
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842
摘要： A semiconductor memory device includes a memory cell array, a spare memory cell array, a first addressing circuit for designating an address of the memory cell array, a second addressing circuit for designating an address of the spare memory cell array, a drive circuit for activating a select line designated by each of the first and second addressing circuits, a program circuit for generating a predetermined output based on whether the memory cell array has a defect or fault or not, and a select circuit responsive to an output from the program circuit for supplying an activation signal to the designated select line at an earlier timing when there is no fault in the memory array cell, and supplying an activation signal delayed by a time necessary for the selection of the spare memory cell array when there is a fault in the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，备用存储单元阵列，用于指定存储单元阵列的地址的第一寻址电路，用于指定备用存储单元阵列的地址的第二寻址电路，用于激活的驱动电路由第一和第二寻址电路中的每一个指定的选择线，用于基于存储单元阵列是否具有缺陷或故障来产生预定输出的程序电路，以及响应于来自程序电路的输出的选择电路，当存储器阵列单元中没有故障时，在更早的定时向指定的选择线提供激活信号，并且当存在故障时提供延迟了选择备用存储单元阵列所需的时间的激活信号存储单元阵列。

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