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1. 发明授权

US07725629B2 Processor array arrangement controlled by control computer 有权
标题翻译：处理器阵列布置由控制计算机控制
公开(公告)号：US07725629B2
公开(公告)日：2010-05-25
申请号：US11554693
申请日：2006-10-31
申请人： Thomas Sturm , Rupert Glaser , Christl Lauterbach , Annelie Sohr , Werner Weber , Frank Schliep
发明人： Thomas Sturm , Rupert Glaser , Christl Lauterbach , Annelie Sohr , Werner Weber , Frank Schliep
IPC分类号： G06F13/12 , G06F15/00 , G06F13/00
CPC分类号： G05B19/0421 , G05B2219/2206 , G05B2219/2224
摘要： A processor arrangement having a plurality of processor units and a control computer. Each of the processor units is connected to at least one adjacent processor unit and has one control element and at least one communications interface for providing a data communications link with an adjacent processor unit. The control computer is connected to one of the processor units, and is configured for exchanging information with the processor unit and for assigning one control element of the plurality of control elements to a device that is electrically connected to the processor arrangement for the control of the device.
摘要翻译：一种具有多个处理器单元和一个控制计算机的处理器装置。每个处理器单元连接到至少一个相邻的处理器单元，并且具有一个控制元件和至少一个用于提供与相邻处理器单元的数据通信链路的通信接口。控制计算机连接到一个处理器单元，并且被配置为与处理器单元交换信息，并且将多个控制元件的一个控制元件分配给电连接到处理器装置的装置，用于控制设备。

2. 发明申请

US20070150071A1 PROCESSOR ARRANGEMENT 有权
标题翻译：加工商安排
公开(公告)号：US20070150071A1
公开(公告)日：2007-06-28
申请号：US11554693
申请日：2006-10-31
申请人： THOMAS STURM , Rupert Glaser , Christl Lauterbach , Annelie Sohr , Werner Weber , Frank Schliep
发明人： THOMAS STURM , Rupert Glaser , Christl Lauterbach , Annelie Sohr , Werner Weber , Frank Schliep
IPC分类号： G05B15/00
CPC分类号： G05B19/0421 , G05B2219/2206 , G05B2219/2224
摘要： A processor arrangement having a plurality of processor units and a control computer. Each of the processor units is connected to at least one adjacent processor unit and has one control element and at least one communications interface for providing a data communications link with an adjacent processor unit. The control computer is connected to one of the processor units, and is configured for exchanging information with the processor unit and for assigning one control element of the plurality of control elements to a device that is electrically connected to the processor arrangement for the control of the device.
摘要翻译：一种具有多个处理器单元和一个控制计算机的处理器装置。每个处理器单元连接到至少一个相邻的处理器单元，并且具有一个控制元件和至少一个用于提供与相邻处理器单元的数据通信链路的通信接口。控制计算机连接到一个处理器单元，并且被配置为与处理器单元交换信息，并且将多个控制元件的一个控制元件分配给电连接到处理器装置的装置，用于控制设备。

3. 发明申请

US20060082440A1 Shelf arrangement and shelf unit 审中-公开
标题翻译：货架布置和货架单元
公开(公告)号：US20060082440A1
公开(公告)日：2006-04-20
申请号：US11251623
申请日：2005-10-14
申请人： Rupert Glaser , Christl Lauterbach , Thomas Sturm
发明人： Rupert Glaser , Christl Lauterbach , Thomas Sturm
IPC分类号： G05B19/00 , G05B23/00 , G06F7/00 , G06F7/04 , G08B29/00 , G06F7/08 , G06Q20/00 , G08C19/00 , H04B1/00 , H04B3/00 , H04Q1/00 , H04Q9/00
CPC分类号： G07F9/026 , G06Q20/201
摘要： A shelf arrangement has a multiplicity of shelf units, each shelf unit having a receiver and a processor coupled thereto. Each receiver is set up to receive data from a data transmission unit fitted on an object which is to be arranged or is arranged in the respective shelf unit. Each processor is set up such that it can determine the position of the shelf unit's processor within the shelf arrangement by virtue of messages being interchanged by processors in directly adjacent shelf units.
摘要翻译：搁架布置具有多个搁架单元，每个搁板单元具有接收器和与其耦合的处理器。每个接收机被设置为从安装在要被布置或布置在相应的搁架单元中的对象上的数据传输单元接收数据。每个处理器被设置成使得它可以通过消息由直接相邻货架单元中的处理器互换来确定货架单元的处理器在货架装置内的位置。

4. 发明申请

US20060035554A1 Textile fabric structure 审中-公开
标题翻译：纺织面料结构
公开(公告)号：US20060035554A1
公开(公告)日：2006-02-16
申请号：US11207599
申请日：2005-08-19
申请人： Rupert Glaser , Stefan Jung , Christl Lauterbach
发明人： Rupert Glaser , Stefan Jung , Christl Lauterbach
IPC分类号： H02G3/04 , D03D15/00
CPC分类号： D03D15/00 , D02G3/441 , D03D1/0088 , D03D15/0066 , D03D15/02 , D10B2101/12 , D10B2101/20 , D10B2401/16 , D10B2401/20 , D10B2503/04 , H05K1/0274 , H05K1/038 , H05K3/284 , H05K2201/0281 , Y10T442/30 , Y10T442/3976
摘要： A textile fabric structure having a plurality of microelectronic components, which are arranged in the textile fabric structure, electrically conductive threads, which couple the plurality of microelectronic components to one another, conductive data transmission threads, which couple the plurality of microelectronic components to one another, and electrically nonconductive threads. The conductive threads and the conductive data transmission threads at the edge of the textile fabric structure are each provided with an electric interface and a data transmission interface.
摘要翻译：布置在纺织织物结构中的具有多个微电子部件的纺织织物结构，将多个微电子部件彼此耦合的导电线，将多个微电子部件彼此耦合的导电数据传输线，和非导电螺纹。纺织物结构边缘处的导电线和导电数据传输线均设有电接口和数据传输接口。

5. 发明授权

US6146992A Vertically integrated semiconductor component and method of producing the same 失效
标题翻译：垂直集成半导体元件及其制造方法
公开(公告)号：US6146992A
公开(公告)日：2000-11-14
申请号：US77074
申请日：1998-05-19
申请人： Christl Lauterbach , Werner Weber
发明人： Christl Lauterbach , Werner Weber
IPC分类号： H01L21/58 , H01L21/768 , H01L21/98 , H01L23/48 , H01L23/522 , H01L23/532 , H01L25/065 , H01L27/00 , H01L23/58
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/53257 , H01L24/29 , H01L24/83 , H01L25/0657 , H01L2224/29111 , H01L2224/2919 , H01L2224/8319 , H01L2224/8385 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/0132 , H01L2924/0665 , H01L2924/07802 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/351
摘要： A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.
摘要翻译： PCT No.PCT / DE96 / 02108 Sec。 371日期1998年5月19日 102（e）日期1998年5月19日PCT 1996年11月6日PCT PCT。第WO97 / 19462号公报日期1997年5月29日垂直集成的半导体部件具有配置在不同基板上的部件级。衬底通过苯并环丁烯的连接层连接，并且通过垂直接触结构在组件水平之间提供电连接。苯并环丁烯连接层提供低应力胶合。

6. 发明授权

US06313517B1 Vertically integrated semiconductor component 有权
标题翻译：垂直集成半导体元件
公开(公告)号：US06313517B1
公开(公告)日：2001-11-06
申请号：US09663462
申请日：2000-09-15
申请人： Christl Lauterbach , Werner Weber
发明人： Christl Lauterbach , Werner Weber
IPC分类号： H01L2940
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/53257 , H01L24/29 , H01L24/83 , H01L25/0657 , H01L2224/29111 , H01L2224/2919 , H01L2224/8319 , H01L2224/8385 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/0132 , H01L2924/0665 , H01L2924/07802 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2924/01047 , H01L2924/0105 , H01L2924/01049 , H01L2924/01079 , H01L2924/0695
摘要： A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.
摘要翻译：提供垂直集成的半导体部件，其具有设置在不同基板上的部件级。衬底通过苯并环丁烯的连接层连接，并且通过垂直接触结构在组件水平之间提供电连接。苯并环丁烯连接层提供低应力胶合。

7. 发明授权

US06833731B1 Electronic circuit for a method for storing information, said circuit comprising ferroelectric flip-flops 失效
标题翻译：用于存储信息的方法的电子电路，所述电路包括铁电触发器
公开(公告)号：US06833731B1
公开(公告)日：2004-12-21
申请号：US10070025
申请日：2002-05-14
申请人： Christl Lauterbach , Georg Braun , Udo Ollert , Werner Weber
发明人： Christl Lauterbach , Georg Braun , Udo Ollert , Werner Weber
IPC分类号： H03K1900
CPC分类号： G01F15/06 , H03K3/356086 , H03K3/45
摘要： A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer period of time or/and in remote sites of use and are dependent upon a supply voltage are impaired with the dependency-related disadvantages, such as the necessity of expensive EEPROMs or significantly increased maintenance expenditure. The present invention relates to an electronic circuit which is provided with an input (5) for inputting at least one information signal, an energy means (2) for converting the energy that is present in the at least one information signal into a supply voltage, a control means (3) for generating at least one switch-on control signal when the information signal is input and a signal processing means (4) for storing information which is represented by the at least one information signal and/or for evaluating information which is represented by the at least one information signal and for storing the secondary information which is obtained by the evaluation. At least one ferroelectric flipflop (26) is used. The signal processing means (4) can be activated by the at least one switch-on control signal for evaluating and/or storing purposes. The at least one information signal can be or is the only energy source for the electronic circuit (1) during the evaluation and/or storing process.
摘要翻译：在用于处理信号的常规电子电路中需要电源电压，例如计数脉冲。电源电压供给逻辑电路元件。特别是必须在更长的时间段内或/和远程使用场所操作并且取决于电源电压的装置会受到依赖性相关缺点的损害，例如昂贵的EEPROM的必要性或显着增加的维护费用。本发明涉及一种电子电路，其具有用于输入至少一个信息信号的输入端（5），用于将存在于至少一个信息信号中的能量转换为电源电压的能量装置（2）用于当输入信息信号时产生至少一个接通控制信号的控制装置（3）和用于存储由至少一个信息信号表示的信息和/或用于评估信息的信息的信号处理装置（4）由所述至少一个信息信号表示，并且用于存储通过评估获得的次要信息。至少使用一个铁电触发器（26）。信号处理装置（4）可以被至少一个接通控制信号激活，用于评估和/或存储目的。在评估和/或存储过程期间，至少一个信息信号可以是或是电子电路（1）的唯一能量源。

8. 发明授权

US5023686A PIN-FET combination with buried p-layer 失效
标题翻译： PIN-FET与掩埋p层组合
公开(公告)号：US5023686A
公开(公告)日：1991-06-11
申请号：US538786
申请日：1990-06-15
申请人： Albrecht Helmut , Christl Lauterbach
发明人： Albrecht Helmut , Christl Lauterbach
IPC分类号： H01L27/14 , H01L27/144
CPC分类号： H01L27/1443
摘要： A PIN-FET combination having a basic layer, a first semiconductor layer as an absorption layer or, resepectively, a buffer layer, a second semiconductor layer as a contact layer or, respectively, as a channel layer and a third semiconductor layer as a cover layer grown surface-wide on a substrate. The p.sup.+ -region of the photodiode and, respectively, the gate region of the FET being fashioned therein. The basic layer is undoped or n-doped in the region of the photodiode and is p-doped in the region of the FET and a surface-wide, p-doped layer portion is present in the region of the FET between the channel layer and the substrate.
摘要翻译：具有碱性层，作为吸收层的第一半导体层或重叠地缓冲层，作为接触层的第二半导体层或分别作为沟道层的第一半导体层和作为覆盖层的第三半导体层的PIN-FET组合在基底上生长表面的层。光电二极管的p +区域和分别形成在其中的FET的栅极区域。基极层在光电二极管的区域是未掺杂的或n掺杂的，并且在FET的区域中被p掺杂，并且表面宽的p掺杂层部分存在于FET的区域中，在沟道层和底物。

9. 发明授权

US07230610B2 Keypad in textiles with capacitive read-out circuit 有权
标题翻译：具有电容读出电路的纺织品中的键盘
公开(公告)号：US07230610B2
公开(公告)日：2007-06-12
申请号：US10868502
申请日：2004-06-14
申请人： Stefan Jung , Christl Lauterbach
发明人： Stefan Jung , Christl Lauterbach
IPC分类号： G09G5/00
CPC分类号： D03D15/00 , D03D1/0088 , D03D15/02 , D10B2101/20 , D10B2401/16 , H01H2203/0085 , H01H2239/006 , H03K17/9622 , H03K2017/9602 , H03K2217/960755 , Y10T428/256
摘要： Input apparatus including at least one textile fabric carrier, at least one flexible, wire-and/or thread-like electrical conductor comprising at least one weft and/or warp thread of the fabric carrier, and at least one electrically conductive, flexible key device which is electrically connected to a key connection of the conductor, wherein the conductor is designed for the connection of an evaluation device.
摘要翻译：输入装置，包括至少一个纺织织物载体，至少一个柔性的，线和/或线状电导体，其包括织物载体的至少一个纬纱和/或经线，以及至少一个导电的，柔性的键装置其电连接到导体的键连接，其中导体被设计用于评估装置的连接。

10. 发明授权

US07005360B2 Method for fabricating a microelectronic circuit including applying metal over and thickening the integrated coil to increase conductivity 有权
标题翻译：一种制造微电子电路的方法，包括将金属涂覆在一起并增厚集成线圈以增加导电性
公开(公告)号：US07005360B2
公开(公告)日：2006-02-28
申请号：US10381406
申请日：2001-10-04
申请人： Christl Lauterbach , Christian Paulus
发明人： Christl Lauterbach , Christian Paulus
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L28/10 , H01L27/08
摘要： A method for fabricating a microelectronic circuit having an improved electrically conductive element. The method includes providing a finished processed microelectronic circuit having a monolithically integrated coil and having a passivation layer situated above at least the monolithically integrated coil. The method further comprises removing at least part of the passivation layer above the monolithically integrated coil and applying a metal layer above the monolithically integrated coil so that the metal layer is electrically coupled to the monolithically integrated coil.
摘要翻译：一种制造具有改进的导电元件的微电子电路的方法。该方法包括提供具有单片集成线圈并具有位于至少单片集成线圈之上的钝化层的成品处理的微电子电路。该方法还包括去除单片集成线圈之上的钝化层的至少一部分，并且在单片集成线圈上方施加金属层，使得金属层电耦合到单片集成线圈。

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