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1. 发明授权

US09734896B2 Circuits and methods for performance optimization of SRAM memory 有权
公开(公告)号：US09734896B2
公开(公告)日：2017-08-15
申请号：US15199167
申请日：2016-06-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Per Torstein Roine , Vinod Menezes , Mahesh Mehendale , Vamsi Gullapalli , Premkumar Seetharaman
IPC分类号： G11C7/12 , G11C11/419 , G11C11/4094 , G11C7/10 , G11C11/412
CPC分类号： G11C11/419 , G11C7/1018 , G11C7/1039 , G11C7/12 , G11C11/4094 , G11C11/412
摘要： In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.

2. 发明申请

US20160163379A1 CIRCUITS AND METHODS FOR PERFORMANCE OPTIMIZATION OF SRAM MEMORY 有权
标题翻译： SRAM存储器性能优化的电路和方法
公开(公告)号：US20160163379A1
公开(公告)日：2016-06-09
申请号：US14562056
申请日：2014-12-05
申请人： Texas Instruments Incorporated
发明人： Per Torstein Roine , Vinod Menezes , Mahesh Mehendale , Vamsi Gullapalli , Premkumar Seetharaman
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C7/1018 , G11C7/1039 , G11C7/12 , G11C11/4094 , G11C11/412
摘要： In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.
摘要翻译：在本申请的各方面中，提供了用于存储数据的电路，其中包括静态随机存取存储器（SRAM）电路，其可操作以将数据存储在以行和列布置的SRAM单元电路阵列中，每个SRAM单元耦合到一对互补位沿着SRAM单元电路的列布置的线以及SRAM存储器电路中的一个或多个预充电电路，其耦合到一对或多对互补位线，并且可操作用于对互补位线对充电至预充电电压，预充电控制信号。 SRAM电路内的预充电控制信号可操作以使SRAM电路内的耦合晶体管响应于从SRAM电路外部的存储器控制器电路输出的模式信号将一对互补位线耦合到预充电电压，指示位线预充电将被执行。

3. 发明授权

US09384826B2 Circuits and methods for performance optimization of SRAM memory 有权
标题翻译： SRAM存储器性能优化的电路和方法
公开(公告)号：US09384826B2
公开(公告)日：2016-07-05
申请号：US14562056
申请日：2014-12-05
申请人： Texas Instruments Incorporated
发明人： Per Torstein Roine , Vinod Menezes , Mahesh Mehendale , Vamsi Gullapalli , Premkumar Seetharaman
IPC分类号： G11C7/12 , G11C11/419 , G11C11/418 , G11C11/4094 , G11C11/412
CPC分类号： G11C11/419 , G11C7/1018 , G11C7/1039 , G11C7/12 , G11C11/4094 , G11C11/412
摘要： In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.
摘要翻译：在本申请的各方面中，提供了用于存储数据的电路，其中包括静态随机存取存储器（SRAM）电路，其可操作以将数据存储在以行和列布置的SRAM单元电路阵列中，每个SRAM单元耦合到一对互补位沿着SRAM单元电路的列布置的线以及SRAM存储器电路中的一个或多个预充电电路，其耦合到一对或多对互补位线，并且可操作用于对互补位线对充电至预充电电压，预充电控制信号。 SRAM电路内的预充电控制信号可操作以使SRAM电路内的耦合晶体管响应于从SRAM电路外部的存储器控制器电路输出的模式信号将一对互补位线耦合到预充电电压，指示位线预充电将被执行。

4. 发明授权

US10423414B2 Parallel processing in hardware accelerators communicably coupled with a processor 有权
公开(公告)号：US10423414B2
公开(公告)日：2019-09-24
申请号：US14539674
申请日：2014-11-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Ajit Deepak Gupte , Mahesh Mehendale , Navin Acharya , Mel Alan Phipps
IPC分类号： G06F9/30 , G06F9/48 , G06F9/38 , G06T1/20
摘要： In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.

5. 发明申请

US20160314832A1 Circuits and Methods for Performance Optimization of SRAM Memory 审中-公开
标题翻译： SRAM存储器性能优化的电路和方法
公开(公告)号：US20160314832A1
公开(公告)日：2016-10-27
申请号：US15199167
申请日：2016-06-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Per Torstein Roine , Vinod Menezes , Mahesh Mehendale , Vamsi Gullapalli , Premkumar Seetharaman
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C7/1018 , G11C7/1039 , G11C7/12 , G11C11/4094 , G11C11/412
摘要： In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.
摘要翻译：在所述示例中，存储器控制器电路控制对SRAM电路的访问。预充电模式控制电路输出：到SRAM电路的突发模式使能信号，指示将沿着选定的一行SRAM单元的一系列SRAM单元被访问; 向SRAM电路提供预充电第一模式信号，指示将发生沿着所选行的第一次访问; 以及向SRAM电路提供预充电最后模式信号，指示将发生沿着所选行的最后访问。 SRAM电路包括以行和列排列以存储数据的SRAM单元的阵列。每个SRAM单元耦合到：沿着一行SRAM单元的相应字线; 和相应的一对互补位线。

6. 发明申请

US20160132329A1 PARALLEL PROCESSING IN HARDWARE ACCELERATORS COMMUNICABLY COUPLED WITH A PROCESSOR 有权
标题翻译：硬件加速器中的并行处理器与处理器通信
公开(公告)号：US20160132329A1
公开(公告)日：2016-05-12
申请号：US14539674
申请日：2014-11-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Ajit Deepak Gupte , Mahesh Mehendale , Navin Acharya , Mel Alan Phipps
IPC分类号： G06F9/30 , G06F9/48
摘要： In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.
摘要翻译：在一个实施例中，公开了一种包括处理器，多个硬件加速器引擎和硬件调度器的设备。处理器被配置为调度多个指令线程的执行，其中每个指令线程包括与执行序列相关联的多个指令。多个硬件加速器引擎执行多个指令线程的调度执行。硬件调度器被配置为控制调度的执行，使得每个硬件加速器引擎被配置为执行相应的指令，并且多个指令由多个硬件加速器引擎以顺序的方式执行。基于执行顺序和多个硬件加速器引擎中的每一个的可用性状态，多个指令线程以并行方式由多个硬件加速器引擎执行。

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