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1. 发明授权

US09081933B2 Methods and apparatus for RC extraction 有权
标题翻译： RC提取的方法和装置
公开(公告)号：US09081933B2
公开(公告)日：2015-07-14
申请号：US14316067
申请日：2014-06-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Te-Yu Liu , Ke-Ying Su , Austin Chingyu Chiang , Hsiao-Shu Chao
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.
摘要翻译：公开了从布局提取电容的方法。该方法将第一网分解为第一和第二分量，并将第二网分解成第三和第四分量。该方法可以通过第一方法获得第一分量和第三分量的第一电容，并且通过与第一方法不同的第二方法获得用于第二分量和第四分量的第二电容。可以提供具有多个条目的库，其中每个条目具有包括第一网络的组件和第二网络的组件的组件对以及组件对的预先计算的电容。第一种方法可能是搜索库以找到预先计算的电容。第二种方法可以是通过方程求解器在飞行中获得第一电容。

2. 发明申请

US20140310675A1 Methods and Apparatus for RC Extraction 审中-公开
标题翻译： RC提取方法与装置
公开(公告)号：US20140310675A1
公开(公告)日：2014-10-16
申请号：US14316067
申请日：2014-06-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Te-Yu Liu , Ke-Ying Su , Austin Chingyu Chiang , Hsiao-Shu Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.
摘要翻译：公开了从布局提取电容的方法。该方法将第一网分解为第一和第二分量，并将第二网分解成第三和第四分量。该方法可以通过第一方法获得第一分量和第三分量的第一电容，并且通过与第一方法不同的第二方法获得用于第二分量和第四分量的第二电容。可以提供具有多个条目的库，其中每个条目具有包括第一网络的组件和第二网络的组件的组件对以及组件对的预先计算的电容。第一种方法可能是搜索库以找到预先计算的电容。第二种方法可以是通过方程求解器在飞行中获得第一电容。

3. 发明授权

US09558314B2 Method of designing circuit layout and system for implementing the same 有权
标题翻译：设计电路布局的方法及其实现方法
公开(公告)号：US09558314B2
公开(公告)日：2017-01-31
申请号：US14580846
申请日：2014-12-23
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Te-Yu Liu , Ke-Ying Su , Cheng Hsiao , Chia-Yi Chen , Ke-Wei Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of designing a circuit layout includes calculating a typical value representing performance characteristics for the circuit layout based on a graphic database system (GDS) file. The method further includes calculating an adjustment value based on the GDS file and at least one of a CAP corner vector or a RES corner vector, wherein the CAP corner vector is based on an eigenvector of a parasitic capacitance of the circuit layout, and the RES corner vector is based on an eigenvector of a parasitic resistance of the circuit layout. The method further includes calculating a corner value based on the typical value and the adjustment value. The method further includes modifying the GDS file if performance characteristics of the corner value fail to satisfy performance requirements of the circuit layout.
摘要翻译：设计电路布局的方法包括基于图形数据库系统（GDS）文件计算表示电路布局的性能特征的典型值。该方法还包括基于GDS文件和CAP角向量或RES角向量中的至少一个来计算调整值，其中CAP角向量基于电路布局的寄生电容的特征向量，RES 角矢量基于电路布局的寄生电阻的特征向量。该方法还包括基于典型值和调整值计算拐角值。该方法还包括如果拐角值的性能特性不能满足电路布局的性能要求，则修改GDS文件。

4. 发明授权

US08793640B1 Methods and apparatus for RC extraction 有权
标题翻译： RC提取的方法和装置
公开(公告)号：US08793640B1
公开(公告)日：2014-07-29
申请号：US13795814
申请日：2013-03-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Te-Yu Liu , Ke-Ying Su , Austin Chingyu Chiang , Hsiao-Shu Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.
摘要翻译：公开了从布局提取电容的方法。该方法将第一网分解为第一和第二分量，并将第二网分解成第三和第四分量。该方法可以通过第一方法获得第一分量和第三分量的第一电容，并且通过与第一方法不同的第二方法获得第二分量和第四分量的第二电容。可以提供具有多个条目的库，其中每个条目具有包括第一网络的组件和第二网络的组件的组件对以及组件对的预先计算的电容。第一种方法可能是搜索库以找到预先计算的电容。第二种方法可以是通过方程求解器在飞行中获得第一电容。

5. 发明授权

US09846761B2 Mask design based on sensitivities to changes in pattern spacing 有权
公开(公告)号：US09846761B2
公开(公告)日：2017-12-19
申请号：US15266621
申请日：2016-09-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chih-Cheng Chou , Te-Yu Liu , Ke-Ying Su , Hsien-Hsin Sean Lee
IPC分类号： G06F17/00 , G06F17/50 , G03F1/00 , G03F1/70
CPC分类号： G06F17/5081 , G03F1/00 , G03F1/70 , G06F17/5009
摘要： A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.

6. 发明授权

US09448467B2 Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same 有权
标题翻译：用于多图案掩模设计的掩模移动电阻 - 电感方法及其执行方法
公开(公告)号：US09448467B2
公开(公告)日：2016-09-20
申请号：US14182859
申请日：2014-02-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chih-Cheng Chou , Te-Yu Liu , Ke-Ying Su , Hsien-Hsin Sean Lee
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G06F17/5081 , G03F1/00 , G03F1/70 , G06F17/5009
摘要： A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.
摘要翻译：一种系统和方法，包括提供集成电路设计的布局，由处理器从所述布局生成多个多个图案化分解，确定所述第一掩模和所述第二掩模之间的最大掩模移位并模拟最坏情况的性能使用在由最大掩模移位限定的范围内的一个或多个掩模移位的多个多个图案化分解中的每一个的值。此外，多个多个图案化分解中的每一个包括分离到第一掩模的图案和多个图案掩模组的第二掩模。

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