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1. 发明申请

US20140245251A1 Design Optimization for Circuit Migration 审中-公开
标题翻译：电路迁移的设计优化
公开(公告)号：US20140245251A1
公开(公告)日：2014-08-28
申请号：US14268845
申请日：2014-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.
摘要翻译：本发明的实施例是一种用于提供集成电路布局的经调整的电子表示的计算机程序产品。计算机程序产品具有其上体现计算机程序的介质。此外，计算机程序包括用于从完整节点网表提供全节点单元的计算机程序代码，用于缩放全节点单元以提供收缩节点单元的计算机程序代码，用于提供全节点单元的定时性能的计算机程序代码和收缩节点单元，用于将全节点单元的定时性能与收缩节点单元的定时性能进行比较的计算机程序代码以及用于提供第一网表的计算机程序代码。

2. 发明授权

US09230052B2 Method of generating a simulation model of a predefined fabrication process 有权
标题翻译：生成预定制造过程的仿真模型的方法
公开(公告)号：US09230052B2
公开(公告)日：2016-01-05
申请号：US14531374
申请日：2014-11-03
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chia-Ming Ho , Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50 , G03F1/36 , G03F1/70 , G03F7/20
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70 , G03F7/70433 , G03F7/70441 , G06F17/5072
摘要： A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design.
摘要翻译：根据样品导电特征产生预定制造工艺的仿真模型的方法包括接收导电特征的几何构型和布局设计。产生基于样品导电特征的几何结构的样品导电特征的电路级仿真模型。硬件处理器将样本导电特征的电路级仿真模型转换成与布局设计的第一组预定标准相对应的第一布局偏差规则和与第一布局偏置规则不同的第二布局偏置规则，对应于布局设计的第二组预定标准。

3. 发明授权

US09361423B2 RC corner solutions for double patterning technology 有权
标题翻译：用于双重图案化技术的RC角解决方案
公开(公告)号：US09361423B2
公开(公告)日：2016-06-07
申请号：US14289782
申请日：2014-05-29
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068
摘要： A method includes selecting a process corner, determining model parameters for forming an integrated circuit, and generating a file using the model parameters for the process corner. The generating the file is performed using a computer. The file includes at least two of a first capacitance table, a second capacitance table, and a third capacitance table. The first capacitance table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks including the layout patterns shift relative to each other. The second capacitance table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The third capacitance table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other.
摘要翻译：一种方法包括选择过程角，确定用于形成集成电路的模型参数，以及使用用于过程角的模型参数生成文件。使用计算机执行生成文件。该文件包括第一电容表，第二电容表和第三电容表中的至少两个。当包括布局图案相对于彼此的布局图案的光刻掩模时，第一电容表存储集成电路的布局图案之间的最大寄生电容。当光刻掩模相对于彼此移动时，第二电容表存储布局图案之间的最小寄生电容。当光刻掩模不相对于彼此移动时，第三电容表存储布局图案之间的标称寄生电容。

4. 发明授权

US09275186B2 Optimization for circuit migration 有权
标题翻译：电路迁移优化
公开(公告)号：US09275186B2
公开(公告)日：2016-03-01
申请号：US14268845
申请日：2014-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment is a method for providing an adjusted electronic representation of an integrated circuit layout, the method including using one or more processor, generating a timing performance of a path in a first netlist, identifying a first cell in the path that violates a timing performance parameter, and generating a plurality of derivative cells from a subsequent cell that is in the path after the first cell, where each derivative cell includes a variation of the subsequent cell. The method further includes in response to the identifying the first cell, replacing the subsequent cell with at least one of the plurality of derivative cells to generate a first modified netlist, where the variation of the at least one of the plurality of derivative cells reduces the violation of the timing performance parameter, and generating a final netlist based on the first modified netlist.
摘要翻译：一个实施例是一种用于提供集成电路布局的经调整的电子表示的方法，所述方法包括使用一个或多个处理器，生成第一网表中的路径的定时性能，识别路径中违反定时性能的第一小区参数，并且从在第一单元之后的路径中的后续单元生成多个衍生单元，其中每个衍生单元包括后续单元的变化。该方法还包括响应于识别第一小区，用多个导数小区中的至少一个替换随后的小区以生成第一修改的网表，其中多个导数小区中的至少一个的变化减少了违反时序性能参数，并且基于第一修改网表生成最终网表。

5. 发明授权

US08671382B2 Method of generating RC technology file 有权
标题翻译：生成RC技术文件的方法
公开(公告)号：US08671382B2
公开(公告)日：2014-03-11
申请号：US13858760
申请日：2013-04-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng , Yung-Chin Hou
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5077 , G06F17/5081
摘要： A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.
摘要翻译：公开了一种产生电阻 - 电容（RC）技术文件的方法。该方法包括从IC铸造接收多个金属方案并将多个金属方案分成一个或多个模块化RC组。该方法还包括识别模块化RC结构; 通过场解算器计算模块RC结构的电容值; 基于不具有互连的各种互连层计算RC结构的等效介电常数和等效高度; 计算所述多个金属方案中的每一种的等效介电常数和等效高度; 以及从所述模块化RC结构的电容值导出所述多个金属方案中的每一个的电容值。

6. 发明申请

US20140258962A1 Parasitic Capacitance Extraction for FinFETs 有权
标题翻译： FinFET的寄生电容提取
公开(公告)号：US20140258962A1
公开(公告)日：2014-09-11
申请号：US13873969
申请日：2013-04-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chia-Ming Ho , Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng , Ze-Ming Wu , Hsien-Hsin Sean Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , H01L21/823821 , H01L21/845 , H01L29/41791
摘要： A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.
摘要翻译：一种方法包括生成三维表。三维表的表格单元包括归一化的寄生电容值，其选自基本上由归一化的多晶对寄生电容值和Fin场效应晶体管（FinFET）的归一化多金属 - 金属 - 接触寄生电容值组成的组）。该三维工作台由FinFET的多金属 - 金属 - 接触间距，FinFET的鳍 - 鳍间距和FinFET的金属 - 接触 - 二 - - - - - - - 间隔来引导。使用计算机执行生成三维表的步骤。

7. 发明授权

US08826213B1 Parasitic capacitance extraction for FinFETs 有权
标题翻译： FinFET的寄生电容提取
公开(公告)号：US08826213B1
公开(公告)日：2014-09-02
申请号：US13873969
申请日：2013-04-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chia-Ming Ho , Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng , Ze-Ming Wu , Hsien-Hsin Sean Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , H01L21/823821 , H01L21/845 , H01L29/41791
摘要： A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.
摘要翻译：一种方法包括生成三维表。三维表的表格单元包括归一化的寄生电容值，其选自基本上由归一化的多晶对寄生电容值和Fin场效应晶体管（FinFET）的归一化多金属 - 金属 - 接触寄生电容值组成的组）。该三维工作台由FinFET的多金属 - 金属 - 接触间距，FinFET的鳍 - 鳍间距和FinFET的金属 - 接触 - 二 - - - - - - - 间隔来引导。使用计算机执行生成三维表的步骤。

8. 发明授权

US08793640B1 Methods and apparatus for RC extraction 有权
标题翻译： RC提取的方法和装置
公开(公告)号：US08793640B1
公开(公告)日：2014-07-29
申请号：US13795814
申请日：2013-03-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Te-Yu Liu , Ke-Ying Su , Austin Chingyu Chiang , Hsiao-Shu Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.
摘要翻译：公开了从布局提取电容的方法。该方法将第一网分解为第一和第二分量，并将第二网分解成第三和第四分量。该方法可以通过第一方法获得第一分量和第三分量的第一电容，并且通过与第一方法不同的第二方法获得第二分量和第四分量的第二电容。可以提供具有多个条目的库，其中每个条目具有包括第一网络的组件和第二网络的组件的组件对以及组件对的预先计算的电容。第一种方法可能是搜索库以找到预先计算的电容。第二种方法可以是通过方程求解器在飞行中获得第一电容。

9. 发明授权

US08726212B1 Streamlined parasitic modeling with common device profile 有权
标题翻译：具有通用设备配置文件的简化寄生建模
公开(公告)号：US08726212B1
公开(公告)日：2014-05-13
申请号：US13773452
申请日：2013-02-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Cheng-I Huang , Chung-Hsing Wang , Hsiao-Shu Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： An embodiment method of streamlining parasitic modeling using a common device profile includes importing, using a processor, a simulated middle end of line (MEOL) profile into a characterization tool, generating, using the processor, a MEOL pattern based on the simulated MEOL profile, import, using the processor, the MEOL pattern and a real profile into a field solver to generate a MEOL capacitance table, updating, using the processor, capacitance data in the characterization tool based on the MEOL capacitance table generated, and generating, using the processor, a resistance and capacitance parasitic extraction technology file using the characterization tool with the capacitance data as updated.
摘要翻译：使用公共设备简档来简化寄生建模的实施例方法包括使用处理器将模拟的中间线（MEOL）简档导入到表征工具中，使用处理器基于模拟的MEOL简档生成MEOL模式，将处理器，MEOL模式和真实简档导入到场求解器中以产生MEOL电容表，基于所生成的MEOL电容表更新使用处理器的表征工具中的电容数据，并使用处理器，电阻和电容寄生提取技术文件使用表征工具与电容数据进行更新。

10. 发明申请

US20130227514A1 Method of Generating RC Technology File 有权
标题翻译：生成RC技术文件的方法
公开(公告)号：US20130227514A1
公开(公告)日：2013-08-29
申请号：US13858760
申请日：2013-04-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng , Yung-Chin Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5081
摘要： A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.
摘要翻译：公开了一种产生电阻 - 电容（RC）技术文件的方法。该方法包括从IC铸造接收多个金属方案并将多个金属方案分成一个或多个模块化RC组。该方法还包括识别模块化RC结构; 通过场解算器计算模块RC结构的电容值; 基于不具有互连的各种互连层计算RC结构的等效介电常数和等效高度; 计算所述多个金属方案中的每一种的等效介电常数和等效高度; 以及从所述模块化RC结构的电容值导出所述多个金属方案中的每一个的电容值。

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