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1. 发明授权

US10985256B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US10985256B2
公开(公告)日：2021-04-20
申请号：US16889781
申请日：2020-06-01
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Ta-Yuan Kung , Ruey-Hsin Liu , Chen-Liang Chu , Chih-Wen Yao , Ming-Ta Lei
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66 , H01L21/762 , H01L29/06
摘要： A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, a pair of source/drain regions, a pair of first well regions, a second well region, a pair of contact regions and a pair of third well regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric. The pair of first well regions are disposed under the pair of source/drain regions. The second well region is disposed between the pair of first well regions. The pair of contact regions are disposed on opposing sides of the pair of source/drain regions. The pair of third well regions are disposed under the pair of contact regions.

2. 发明授权

US10686047B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US10686047B2
公开(公告)日：2020-06-16
申请号：US15987318
申请日：2018-05-23
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Ta-Yuan Kung , Ruey-Hsin Liu , Chen-Liang Chu , Chih-Wen Yao , Ming-Ta Lei
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66 , H01L21/762 , H01L29/06
摘要： A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.

3. 发明授权

US09224827B2 High voltage resistor 有权
标题翻译：高压电阻
公开(公告)号：US09224827B2
公开(公告)日：2015-12-29
申请号：US14074435
申请日：2013-11-07
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L21/20 , H01L29/66 , H01L23/522 , H01L27/02 , H01L27/08
CPC分类号： H01L29/66166 , H01L23/5228 , H01L27/0288 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.
摘要翻译：提供一种半导体器件。半导体器件包括电阻器和电压保护器件。电阻器具有螺旋形状。电阻器具有第一部分和第二部分。电压保护装置包括电耦合到电阻器的第一部分的第一掺杂区域。电压保护装置包括电耦合到电阻器的第二部分的第二掺杂区域。第一和第二掺杂区具有相反的掺杂极性。

4. 发明授权

US09070663B2 Method and apparatus for forming a semiconductor gate 有权
标题翻译：用于形成半导体栅极的方法和装置
公开(公告)号：US09070663B2
公开(公告)日：2015-06-30
申请号：US13968507
申请日：2013-08-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Chen-Liang Chu , Fei-Yuh Chen , Chih-Wen Yao
IPC分类号： H01L21/3205 , H01L29/423 , H01L29/66 , H01L29/78 , H01L21/00 , H01L29/06
CPC分类号： H01L29/4238 , H01L29/0619 , H01L29/0653 , H01L29/401 , H01L29/42316 , H01L29/42376 , H01L29/66477 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.
摘要翻译：本公开提供了一种用于制造半导体栅极的装置和方法。该装置包括：具有有源区和与该有源区形成界面的电介质区的衬底; 位于所述有源区的一部分上方的栅电极和所述电介质区的一部分; 以及设置在所述栅电极内的介电材料，所述电介质材料设置在所述有源区和所述电介质区之间的界面附近。该方法包括：提供具有与活性区形成界面的有源区和电介质区的衬底; 在所述衬底上形成栅电极，所述栅电极在所述界面之上的所述栅电极的区域附近具有开口; 并用介电材料填充开口。

5. 发明申请

US20130337644A1 Method and Apparatus for Forming a Semiconductor Gate 有权
标题翻译：用于形成半导体栅极的方法和装置
公开(公告)号：US20130337644A1
公开(公告)日：2013-12-19
申请号：US13968507
申请日：2013-08-16
申请人： Taiwan Semiconductor Manufacturing Company, LTD
发明人： Chen-Liang Chu , Fei-Yuh Chen , Chih-Wen Yao
IPC分类号： H01L29/423
CPC分类号： H01L29/4238 , H01L29/0619 , H01L29/0653 , H01L29/401 , H01L29/42316 , H01L29/42376 , H01L29/66477 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.
摘要翻译：本公开提供了一种用于制造半导体栅极的装置和方法。该装置包括：具有有源区和与该有源区形成界面的电介质区的衬底; 位于所述有源区的一部分上方的栅电极和所述电介质区的一部分; 以及设置在所述栅电极内的介电材料，所述电介质材料设置在所述有源区和所述电介质区之间的界面附近。该方法包括：提供具有与活性区形成界面的有源区和电介质区的衬底; 在所述衬底上形成栅电极，所述栅电极在所述界面之上的所述栅电极的区域附近具有开口; 并用介电材料填充开口。

6. 发明授权

US11967645B2 Power MOSFETs structure 有权
公开(公告)号：US11967645B2
公开(公告)日：2024-04-23
申请号：US17390565
申请日：2021-07-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Yogendra Yadav , Chi-Chih Chen , Ruey-Hsin Liu , Chih-Wen Yao
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/423 , H01L29/51 , H01L29/66 , H01L27/07
CPC分类号： H01L29/7823 , H01L29/0865 , H01L29/0882 , H01L29/1095 , H01L29/402 , H01L29/42356 , H01L29/42368 , H01L29/42376 , H01L29/512 , H01L29/66659 , H01L29/66681 , H01L29/7835 , H01L27/0733 , H01L29/0847
摘要： A semiconductor device is provided. The semiconductor device includes a substrate, a field plate, a gate electrode, and a first dielectric layer. The substrate has a top surface. The substrate includes a first drift region with a first conductivity type extending from the top surface of the substrate into the substrate, and includes a second drill region with the first conductivity type extending from the top surface of the substrate into the substrate and adjacent to the first drift region. The field plate is over the substrate. The gate electrode has a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate. The first dielectric layer is between the substrate and the field plate. The first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate.

7. 发明授权

US10381259B2 Semiconductor device with localized carrier lifetime reduction and fabrication method thereof 有权
公开(公告)号：US10381259B2
公开(公告)日：2019-08-13
申请号：US15614030
申请日：2017-06-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Alex Kalnitsky , Chih-Wen Yao , Jun Cai , Ruey-Hsin Liu , Hsiao-Chin Tuan
IPC分类号： H01L21/265 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L21/8234 , H01L29/10
摘要： A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.

8. 发明公开

US20240250188A1 REDUCED SURFACE FIELD LAYER IN VARACTOR 审中-公开
公开(公告)号：US20240250188A1
公开(公告)日：2024-07-25
申请号：US18624264
申请日：2024-04-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Liang-Yu Su , Chih-Wen Yao , Hsiao-Chin Tuan , Ming-Ta Lei
IPC分类号： H01L29/93 , H01L27/08 , H01L29/06 , H01L29/66
CPC分类号： H01L29/93 , H01L27/0808 , H01L29/063 , H01L29/66174
摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a first doped region in a substrate and comprising a first doping type. A gate structure is over the first doped region. A pair of contact regions are in the substrate on opposing sides of the gate structure and comprising the first doping type. The first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions. A second doped region is in the substrate and along a bottom of the first doped region. The second doped region comprises a second doping type opposite the first doping type.

9. 发明授权

US08779505B2 Quasi-vertical structure for high voltage MOS device 有权
标题翻译：高电压MOS器件的准垂直结构
公开(公告)号：US08779505B2
公开(公告)日：2014-07-15
申请号：US13875698
申请日：2013-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao Chin Tuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device which includes a buried layer having a first dopant type disposed in a substrate. The semiconductor device further includes a second layer having the first dopant type over the buried layer, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the second layer. The semiconductor device further includes a first well of a second dopant type disposed in the second layer and a first source region of the first dopant type disposed in the first well and connected to a source contact on one side. The semiconductor device further includes a gate disposed on top of the well and the second layer and a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the second layer and the first well by an insulation layer.
摘要翻译：一种半导体器件，其包括设置在衬底中的具有第一掺杂剂类型的掩埋层。半导体器件还包括在掩埋层上具有第一掺杂剂类型的第二层，其中掩埋层的掺杂剂浓度高于第二层的掺杂剂浓度。半导体器件还包括布置在第二层中的第二掺杂剂型的第一阱和设置在第一阱中的第一掺杂剂类型的第一源极区域，并在一侧连接到源极接触。半导体器件还包括设置在阱和第二层的顶部上的栅极和从掩埋层延伸到漏极接触的金属电极，其中金属电极通过绝缘层与第二层和第一阱绝缘。

10. 发明授权

US10672904B2 Power MOSFETs and methods for manufacturing the same 审中-公开
公开(公告)号：US10672904B2
公开(公告)日：2020-06-02
申请号：US16389664
申请日：2019-04-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Yogendra Yadav , Chi-Chih Chen , Ruey-Hsin Liu , Chih-Wen Yao
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/51 , H01L27/07
摘要： A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.

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