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1. 发明授权

US08779505B2 Quasi-vertical structure for high voltage MOS device 有权
标题翻译：高电压MOS器件的准垂直结构
公开(公告)号：US08779505B2
公开(公告)日：2014-07-15
申请号：US13875698
申请日：2013-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao Chin Tuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device which includes a buried layer having a first dopant type disposed in a substrate. The semiconductor device further includes a second layer having the first dopant type over the buried layer, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the second layer. The semiconductor device further includes a first well of a second dopant type disposed in the second layer and a first source region of the first dopant type disposed in the first well and connected to a source contact on one side. The semiconductor device further includes a gate disposed on top of the well and the second layer and a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the second layer and the first well by an insulation layer.
摘要翻译：一种半导体器件，其包括设置在衬底中的具有第一掺杂剂类型的掩埋层。半导体器件还包括在掩埋层上具有第一掺杂剂类型的第二层，其中掩埋层的掺杂剂浓度高于第二层的掺杂剂浓度。半导体器件还包括布置在第二层中的第二掺杂剂型的第一阱和设置在第一阱中的第一掺杂剂类型的第一源极区域，并在一侧连接到源极接触。半导体器件还包括设置在阱和第二层的顶部上的栅极和从掩埋层延伸到漏极接触的金属电极，其中金属电极通过绝缘层与第二层和第一阱绝缘。

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