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1. 发明申请

US20060189099A1 Method of cutting integrated circuit chips from wafer by ablating with laser and cutting with saw blade 有权
标题翻译：通过激光切割和锯片切割从晶片切割集成电路芯片的方法
公开(公告)号：US20060189099A1
公开(公告)日：2006-08-24
申请号：US11174710
申请日：2005-07-05
申请人： Szu Lu , Hsin-Hui Lee , Ming-Chung Sung , Mirng-Ji Lii
发明人： Szu Lu , Hsin-Hui Lee , Ming-Chung Sung , Mirng-Ji Lii
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13116 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of cutting an integrated circuit chip from a wafer having a plurality of integrated circuit chips is provided. An upper portion of the wafer is ablated using two laser beams to form two substantially parallel trenches that extend into the wafer from a top surface of the wafer through intermetal dielectric layers and at least partially into a substrate of the wafer. After the ablating to form the two trenches, cutting through the wafer between outer sidewalls of the two laser-ablated trenches with a saw blade is performed. A width between the outer sidewalls of the two laser-ablated trenches is greater than a cutting width of the saw blade. This may be particularly useful in lead-free packaging applications and/or applications where the intermetal dielectric layers use low-k dielectric materials, for example.
摘要翻译：提供了从具有多个集成电路芯片的晶片切割集成电路芯片的方法。使用两个激光束来消除晶片的上部，以形成两个基本上平行的沟槽，其从晶片的顶表面穿过金属间电介质层并且至少部分地延伸到晶片的衬底中延伸到晶片中。在消融以形成两个沟槽之后，执行用锯片在两个激光烧蚀的沟槽的外侧壁之间切割晶片。两个激光烧蚀沟槽的外侧壁之间的宽度大于锯片的切割宽度。这对于例如在金属间电介质层使用低k电介质材料的无铅封装应用和/或应用中尤其有用。

2. 发明申请

US20070257365A1 Packaged Semiconductor Chip Comprising An Integrated Circuit Chip Ablated With Laser And Cut With Saw Blade From Wafer 有权
标题翻译：封装的半导体芯片包括一个集成电路芯片，激光切割与锯片从晶片切割
公开(公告)号：US20070257365A1
公开(公告)日：2007-11-08
申请号：US11777878
申请日：2007-07-13
申请人： Szu Wei Lu , Hsin-Hui Lee , Ming-Chung Sung , Mirng-Ji Lii
发明人： Szu Wei Lu , Hsin-Hui Lee , Ming-Chung Sung , Mirng-Ji Lii
IPC分类号： H01L23/48
CPC分类号： H01L21/78 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13116 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.
摘要翻译：一种封装半导体芯片，包括具有低k电介质层和芯片基板的集成电路芯片，其中所述集成电路芯片的边缘具有第一边缘部分和第二边缘部分。所述第一边缘部分的至少一部分与所述低k电介质层相同，并且所述第一边缘部分被激光烧蚀以在其中形成一系列圆形凹陷。所述第二边缘部分与所述芯片基板的至少一部分处于相同的高度，并且所述第二边缘部分具有与所述第一边缘部分不同的表面纹理。封装的半导体芯片还包括具有附接的集成电路芯片的封装基板和电连接在封装基板和集成电路芯片之间的多个焊料凸块。

3. 发明授权

US07265034B2 Method of cutting integrated circuit chips from wafer by ablating with laser and cutting with saw blade 有权
标题翻译：通过激光切割和锯片切割从晶片切割集成电路芯片的方法
公开(公告)号：US07265034B2
公开(公告)日：2007-09-04
申请号：US11174710
申请日：2005-07-05
申请人： Szu Wei Lu , Hsin-Hui Lee , Ming-Chung Sung , Mirng-Ji Lii
发明人： Szu Wei Lu , Hsin-Hui Lee , Ming-Chung Sung , Mirng-Ji Lii
IPC分类号： H01L21/46
CPC分类号： H01L21/78 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13116 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of cutting an integrated circuit chip from a wafer having a plurality of integrated circuit chips is provided. An upper portion of the wafer is ablated using two laser beams to form two substantially parallel trenches that extend into the wafer from a top surface of the wafer through intermetal dielectric layers and at least partially into a substrate of the wafer. After the ablating to form the two trenches, cutting through the wafer between outer sidewalls of the two laser-ablated trenches with a saw blade is performed. A width between the outer sidewalls of the two laser-ablated trenches is greater than a cutting width of the saw blade. This may be particularly useful in lead-free packaging applications and/or applications where the intermetal dielectric layers use low-k dielectric materials, for example.
摘要翻译：提供了从具有多个集成电路芯片的晶片切割集成电路芯片的方法。使用两个激光束来消除晶片的上部，以形成两个基本上平行的沟槽，其从晶片的顶表面穿过金属间电介质层并且至少部分地延伸到晶片的衬底中延伸到晶片中。在消融以形成两个沟槽之后，执行用锯片在两个激光烧蚀的沟槽的外侧壁之间切割晶片。两个激光烧蚀沟槽的外侧壁之间的宽度大于锯片的切割宽度。这对于例如在金属间电介质层使用低k电介质材料的无铅封装应用和/或应用中尤其有用。

4. 发明授权

US07642631B2 Packaged semiconductor chip comprising an integrated circuit chip ablated with laser and cut with saw blade from wafer 有权
标题翻译：封装的半导体芯片包括用激光烧蚀的集成电路芯片，并从晶片切割锯片
公开(公告)号：US07642631B2
公开(公告)日：2010-01-05
申请号：US11777878
申请日：2007-07-13
申请人： Szu Wei Lu , Hsin-Hui Lee , Ming-Chung Sung , Mirng-Ji Lii
发明人： Szu Wei Lu , Hsin-Hui Lee , Ming-Chung Sung , Mirng-Ji Lii
IPC分类号： H01L23/02
CPC分类号： H01L21/78 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13116 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.
摘要翻译：一种封装半导体芯片，包括具有低k电介质层和芯片基板的集成电路芯片，其中所述集成电路芯片的边缘具有第一边缘部分和第二边缘部分。所述第一边缘部分的至少一部分与所述低k电介质层相同，并且所述第一边缘部分被激光烧蚀以在其中形成一系列圆形凹陷。所述第二边缘部分与所述芯片基板的至少一部分处于相同的高度，并且所述第二边缘部分具有与所述第一边缘部分不同的表面纹理。封装的半导体芯片还包括具有附接的集成电路芯片的封装基板和电连接在封装基板和集成电路芯片之间的多个焊料凸块。

5. 发明申请

US20140004660A1 System and Method for Forming Uniform Rigid Interconnect Structures 有权
标题翻译：形成均匀刚性互连结构的系统和方法
公开(公告)号：US20140004660A1
公开(公告)日：2014-01-02
申请号：US13539188
申请日：2012-06-29
申请人： Ming-Chung Sung , Yung Ching Chen , Chien-Hsiun Lee , Chen-Hua Yu , Mirng-Ji Lii
发明人： Ming-Chung Sung , Yung Ching Chen , Chien-Hsiun Lee , Chen-Hua Yu , Mirng-Ji Lii
IPC分类号： H01L21/50
CPC分类号： H01L21/4825 , H01L21/4853 , H01L23/49811 , H01L24/11 , H01L24/742 , H01L24/78 , H01L2224/1134 , H01L2224/45144 , H01L2224/742 , H01L2224/78 , H01L2224/78301 , H01L2924/12042 , H01L2924/00014 , H01L2924/00
摘要： Disclosed herein is a system and method for mounting semiconductor packages by forming one or more interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a target package. Mounting the interconnect may comprise ultrasonically welding the interconnects to the mounting pads, and the interconnect may be mounted via a mounting node on the end of the interconnect, wherein the mounting node may be formed by an electric flame off process. The interconnects may be trimmed to one or more substantially uniform heights, optionally using a laser or contact-type trimming system, and the tails of the interconnects may be supported during trimming. A top package may be bonded on the trimmed ends of the interconnects. During mounting, a support plate may be used to support the package, and a mask maybe used during interconnect mounting.
摘要翻译：本文公开了一种用于通过形成一个或多个互连件，可选地用引线键合器安装半导体封装以及将互连件安装到目标封装上的安装焊盘来安装半导体封装件的系统和方法。安装互连可以包括将互连件超声波焊接到安装焊盘，并且互连可以经由互连端部上的安装节点来安装，其中安装节点可以由电火焰熄灭工艺形成。互连可以被修剪到一个或多个基本均匀的高度，可选地使用激光或接触式修剪系统，并且在修剪期间可以支撑互连的尾部。顶部封装可以结合在互连件的修剪端上。在安装期间，可以使用支撑板来支撑封装，并且在互连安装期间可以使用掩模。

6. 发明申请

US20130168856A1 Package on Package Devices and Methods of Packaging Semiconductor Dies 有权
标题翻译：封装器件封装和封装半导体芯片的方法
公开(公告)号：US20130168856A1
公开(公告)日：2013-07-04
申请号：US13493862
申请日：2012-06-11
申请人： Tsung-Ding Wang , Ming-Chung Sung , Jiun Yi Wu , Chien-Hsun Lee , Mirng-Ji Lii
发明人： Tsung-Ding Wang , Ming-Chung Sung , Jiun Yi Wu , Chien-Hsun Lee , Mirng-Ji Lii
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L21/563 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2924/15321 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012
摘要： Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die.
摘要翻译：封装封装（PoP）器件和封装半导体管芯的方法被公开。 PoP器件包括底部封装的芯片，其具有设置在其顶表面上的焊球，以及顶部封装的管芯，其具有设置在其底表面上的金属突起凸块。金属柱凸起包括凸起区域和耦合到凸起区域的尾部区域。顶部封装模具上的每个金属柱形凸块与底部封装模具上的一个焊球相连。

7. 发明授权

US08796132B2 System and method for forming uniform rigid interconnect structures 有权
标题翻译：用于形成均匀刚性互连结构的系统和方法
公开(公告)号：US08796132B2
公开(公告)日：2014-08-05
申请号：US13539188
申请日：2012-06-29
申请人： Ming-Chung Sung , Yung Ching Chen , Chien-Hsun Lee , Chen-Hua Yu , Mirng-Ji Lii
发明人： Ming-Chung Sung , Yung Ching Chen , Chien-Hsun Lee , Chen-Hua Yu , Mirng-Ji Lii
IPC分类号： H01L21/60 , H01L21/48
CPC分类号： H01L21/4825 , H01L21/4853 , H01L23/49811 , H01L24/11 , H01L24/742 , H01L24/78 , H01L2224/1134 , H01L2224/45144 , H01L2224/742 , H01L2224/78 , H01L2224/78301 , H01L2924/12042 , H01L2924/00014 , H01L2924/00
摘要： Disclosed herein is a system and method for mounting semiconductor packages by forming one or more interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a target package. Mounting the interconnect may comprise ultrasonically welding the interconnects to the mounting pads, and the interconnect may be mounted via a mounting node on the end of the interconnect, wherein the mounting node may be formed by an electric flame off process. The interconnects may be trimmed to one or more substantially uniform heights, optionally using a laser or contact-type trimming system, and the tails of the interconnects may be supported during trimming. A top package may be bonded on the trimmed ends of the interconnects. During mounting, a support plate may be used to support the package, and a mask maybe used during interconnect mounting.
摘要翻译：本文公开了一种用于通过形成一个或多个互连件，可选地用引线键合器安装半导体封装以及将互连件安装到目标封装上的安装焊盘来安装半导体封装件的系统和方法。安装互连可以包括将互连件超声波焊接到安装焊盘，并且互连可以经由互连端部上的安装节点来安装，其中安装节点可以由电火焰熄灭工艺形成。互连可以被修剪到一个或多个基本均匀的高度，可选地使用激光或接触式修剪系统，并且在修剪期间可以支撑互连的尾部。顶部封装可以结合在互连件的修剪端上。在安装期间，可以使用支撑板来支撑封装，并且在互连安装期间可以使用掩模。

8. 发明授权

US08823180B2 Package on package devices and methods of packaging semiconductor dies 有权
标题翻译：封装器件封装以及封装半导体管芯的方法
公开(公告)号：US08823180B2
公开(公告)日：2014-09-02
申请号：US13493862
申请日：2012-06-11
申请人： Tsung-Ding Wang , Ming-Chung Sung , Jiun Yi Wu , Chien-Hsiun Lee , Mirng-Ji Lii
发明人： Tsung-Ding Wang , Ming-Chung Sung , Jiun Yi Wu , Chien-Hsiun Lee , Mirng-Ji Lii
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/563 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2924/15321 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012
摘要： Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die.
摘要翻译：封装封装（PoP）器件和封装半导体管芯的方法被公开。 PoP器件包括底部封装的芯片，其具有设置在其顶表面上的焊球，以及顶部封装的管芯，其具有设置在其底表面上的金属突起凸块。金属柱凸起包括凸起区域和耦合到凸起区域的尾部区域。顶部封装模具上的每个金属柱形凸块与底部封装模具上的一个焊球相连。

9. 发明申请

US20130093094A1 Method and Apparatus for Die Assembly 有权
标题翻译：模具组装方法与装置
公开(公告)号：US20130093094A1
公开(公告)日：2013-04-18
申请号：US13276184
申请日：2011-10-18
申请人： Ming-Chung Sung , Yu-Chih Liu , Wei-Ting Lin , Chien-Hsiun Lee
发明人： Ming-Chung Sung , Yu-Chih Liu , Wei-Ting Lin , Chien-Hsiun Lee
IPC分类号： H01L23/48 , H01L21/78
CPC分类号： H01L23/3114 , H01L21/561 , H01L21/6836 , H01L21/78 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/73104
摘要： Methods and apparatus for die assembly. A method includes forming a trench extending from an active surface of a semiconductor substrate comprising a plurality of integrated circuit dies having connector terminals extending from the active surface, the trench extending into, but not through, the semiconductor substrate; forming a protective layer overlying the active surface of the semiconductor substrate and the trench, and covering the lower portion of the connector terminals; opening a pre-dicing opening in the protective layer and within the trench; applying a tape over the active surface of the semiconductor wafer, the protective layer and the connector terminals; and performing an operation on a backside of the semiconductor substrate to remove material until the pre-dicing opening is exposed on the backside of the semiconductor wafer. An apparatus includes a semiconductor substrate with integrated circuits and a protective layer surrounding connector terminals of integrated circuits.
摘要翻译：模具组装的方法和装置一种方法包括形成从半导体衬底的有源表面延伸的沟槽，其包括多个集成电路管芯，所述多个集成电路管芯具有从所述有源表面延伸的连接器端子，形成覆盖在半导体衬底和沟槽的有源表面上的保护层，并覆盖连接器端子的下部; 在保护层和沟槽内打开预切割开口; 在半导体晶片的有源表面，保护层和连接器端子上施加带; 以及在半导体衬底的背面进行操作以去除材料，直到在半导体晶片的背面露出预切割开口。一种装置包括具有集成电路的半导体衬底和围绕集成电路的连接器端子的保护层。

10. 发明授权

US07977155B2 Wafer-level flip-chip assembly methods 有权
标题翻译：晶圆级倒装芯片组装方法
公开(公告)号：US07977155B2
公开(公告)日：2011-07-12
申请号：US11800386
申请日：2007-05-04
申请人： Chien-Hsiun Lee , Clinton Chao , Ming-Chung Sung , Tjandra Winata Karta
发明人： Chien-Hsiun Lee , Clinton Chao , Ming-Chung Sung , Tjandra Winata Karta
IPC分类号： H01L21/00 , H01L21/66
CPC分类号： H01L24/97 , H01L21/563 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/30 , H01L24/81 , H01L24/83 , H01L24/94 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2224/83192 , H01L2224/83194 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/00 , H01L2224/0401
摘要： A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors.
摘要翻译：提供一种封装集成电路结构的方法。该方法包括在晶片的表面上提供具有接合导体的晶片，并将化合物底部填充物施加到晶片的表面上。复合底层填充物包括底部填充材料和助焊剂材料。然后，在施加化合物底部填充物的步骤之后，将晶片接合在晶片上，其中在该芯片上的焊料凸块与接合导体接合。

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