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1. 发明申请

US20160341795A1 Scheme for Masking Output of Scan Chains in Test Circuit 审中-公开
标题翻译：测试电路中扫描链屏蔽输出方案
公开(公告)号：US20160341795A1
公开(公告)日：2016-11-24
申请号：US15230860
申请日：2016-08-08
申请人： Synopsys, Inc.
发明人： Anshuman Chandra , Subramanian B. Chebiyam , Jyotirmoy Saikia , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3177 , G01R31/317
摘要： Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.
摘要翻译：操作集成电路的测试电路的扫描链，以将压缩机单个扇出或多个扇出。测试电路接收用于配置扫描链的扇出的扇出控制信号。如果扇出控制信号指示使用单扇区配置扫描链，则将扫描链的输出发送到压缩器的一个输入。如果扇出控制信号指示以多扇出配置扫描链，则将扫描链的输出发送到压缩机的多个输入。

2. 发明授权

US09417287B2 Scheme for masking output of scan chains in test circuit 有权
标题翻译：用于屏蔽测试电路中扫描链输出的方案
公开(公告)号：US09417287B2
公开(公告)日：2016-08-16
申请号：US14254423
申请日：2014-04-16
申请人： Synopsys, Inc.
发明人： Anshuman Chandra , Subramanian B. Chebiyam , Jyotirmoy Saikia , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3185 , G01R31/3177 , G06F11/27 , G01R31/3187
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/3185 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318566 , G01R31/3187 , G06F11/27
摘要： Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.
摘要翻译：操作集成电路的测试电路的扫描链，以将压缩机单个扇出或多个扇出。测试电路接收用于配置扫描链的扇出的扇出控制信号。如果扇出控制信号指示使用单扇区配置扫描链，则将扫描链的输出发送到压缩器的一个输入。如果扇出控制信号指示以多扇出配置扫描链，则将扫描链的输出发送到压缩机的多个输入。

3. 发明申请

US20140317463A1 Scheme for Masking Output of Scan Chains in Test Circuit 有权
标题翻译：测试电路中扫描链屏蔽输出方案
公开(公告)号：US20140317463A1
公开(公告)日：2014-10-23
申请号：US14254423
申请日：2014-04-16
申请人： Synopsys, Inc.
发明人： Anshuman Chandra , Subramanian B. Chebiyam , Jyotirmoy Saikia , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/3185 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318566 , G01R31/3187 , G06F11/27
摘要： Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.
摘要翻译：操作集成电路的测试电路的扫描链，以将压缩机单个扇出或多个扇出。测试电路接收用于配置扫描链的扇出的扇出控制信号。如果扇出控制信号指示使用单扇区配置扫描链，则将扫描链的输出发送到压缩器的一个输入。如果扇出控制信号指示以多扇出配置扫描链，则将扫描链的输出发送到压缩机的多个输入。

4. 发明授权

US09239897B2 Hierarchical testing architecture using core circuit with pseudo-interfaces 有权
标题翻译：具有伪接口的核心电路的分层测试架构
公开(公告)号：US09239897B2
公开(公告)日：2016-01-19
申请号：US14243602
申请日：2014-04-02
申请人： Synopsys, Inc.
发明人： Subramanian B. Chebiyam , Santosh Kulkarni , Anshuman Chandra , Rohit Kapur
IPC分类号： G06F17/50 , G01R31/3185
CPC分类号： G06F17/5045 , G01R31/318547
摘要： A core circuit that can be connected in a hierarchical manner, and configured to test a multiple circuits is disclosed. The core circuit includes at least one real input for receiving scan-in data for controlling operation of the core circuit. The core circuit further includes an input register coupled to the at least one real input and configured to store data. The core circuit further includes at least one scan chain coupled a subset if registers of the register chain and configured to generate scan-out data representing the presence of faults in an circuit. Furthermore, the core circuit includes at least one control pseudo-output coupled to the input register and configured to route at least a subset of the data to another register chain in the core circuit or to another core circuit.
摘要翻译：公开了可以以分层方式连接并被配置为测试多个电路的核心电路。核心电路包括至少一个实际输入，用于接收用于控制核心电路的操作的扫描数据。核心电路还包括耦合到至少一个实际输入并被配置为存储数据的输入寄存器。核心电路还包括至少一个扫描链，其耦合子集，如果寄存器链的寄存器并被配置为产生表示电路中存在故障的扫描数据。此外，核心电路包括耦合到输入寄存器的至少一个控制伪输出，并被配置为将数据的至少一个子集路由到核心电路中的另一个寄存器链或另一个核心电路。

5. 发明申请

US20140304672A1 Hierarchical Testing Architecture Using Core Circuit with Pseudo-Interfaces 有权
标题翻译：使用具有伪接口的核心电路的分层测试体系结构
公开(公告)号：US20140304672A1
公开(公告)日：2014-10-09
申请号：US14243602
申请日：2014-04-02
申请人： Synopsys, Inc.
发明人： Subramanian B. Chebiyam , Santosh Kulkarni , Anshuman Chandra , Rohit Kapur
IPC分类号： G01R31/3177 , G06F17/50
CPC分类号： G06F17/5045 , G01R31/318547
摘要： A core circuit that can be connected in a hierarchical manner, and configured to test a multiple circuits is disclosed. The core circuit includes at least one real input for receiving scan-in data for controlling operation of the core circuit. The core circuit further includes an input register coupled to the at least one real input and configured to store data. The core circuit further includes at least one scan chain coupled a subset if registers of the register chain and configured to generate scan-out data representing the presence of faults in an circuit. Furthermore, the core circuit includes at least one control pseudo-output coupled to the input register and configured to route at least a subset of the data to another register chain in the core circuit or to another core circuit.
摘要翻译：公开了可以以分层方式连接并被配置为测试多个电路的核心电路。核心电路包括至少一个实际输入，用于接收用于控制核心电路的操作的扫描数据。核心电路还包括耦合到至少一个实际输入并被配置为存储数据的输入寄存器。核心电路还包括至少一个扫描链，其耦合子集，如果寄存器链的寄存器并被配置为产生表示电路中存在故障的扫描数据。此外，核心电路包括耦合到输入寄存器的至少一个控制伪输出，并被配置为将数据的至少一个子集路由到核心电路中的另一个寄存器链或另一个核心电路。

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