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1. 发明申请

US20140289579A1 Reordering or Removal of Test Patterns for Detecting Faults in Integrated Circuit 有权
标题翻译：检测集成电路故障的测试模式的重新排序或删除
公开(公告)号：US20140289579A1
公开(公告)日：2014-09-25
申请号：US14222485
申请日：2014-03-21
申请人： Synopsys, Inc.
发明人： Sushovan Podder , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3177
CPC分类号： G01R31/318547 , G01R31/31835
摘要： A method for reordering a test pattern set for testing an integrated circuit is disclosed. A productivity index is computed for each test pattern in a test pattern set. The productivity index of a first test pattern and the productivity index of a second test pattern are compared. If the productivity index of the second test pattern is larger than the productivity index of the first test pattern, the location of the first test pattern and the second test pattern are swapped.
摘要翻译：公开了一种用于重新排列用于测试集成电路的测试图案集的方法。针对测试模式集中的每个测试模式计算生产率指数。比较第一测试模式的生产率指数和第二测试模式的生产率指数。如果第二测试图形的生产率指数大于第一测试图形的生产率指数，则交换第一测试图案和第二测试图案的位置。

2. 发明授权

US09568550B1 Identifying failure indicating scan test cells of a circuit-under-test 有权
标题翻译：识别失败电路的扫描测试单元的故障
公开(公告)号：US09568550B1
公开(公告)日：2017-02-14
申请号：US14835650
申请日：2015-08-25
申请人： Synopsys, Inc.
发明人： Subhadip Kundu , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/317
CPC分类号： G01R31/318566 , G01R31/318547
摘要： A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature and mapping at least a predefined minimum number of error signatures to respective scan test cells of the plurality of scan test cells. For each error signature, a priority of the mapping is determined by the signature type the respective error signature has been assigned to.
摘要翻译：所公开的配置用于识别至少一个故障指示被测电路CUT的扫描测试单元，具有多个扫描测试单元的CUT。该配置包括通过CUT的压缩器生成多个错误签名，其中多个错误签名的每个错误签名由包括至少一个故障指示位的相应的位序列组成，将每个错误签名分配给至少第一，第二和第三签名类型，根据指示相应错误签名的比特的故障总数，并将至少预定义的最小数量的错误签名映射到多个扫描测试单元中的各个扫描测试单元。对于每个错误签名，映射的优先级由相应错误签名已被分配给的签名类型来确定。

3. 发明申请

US20160341795A1 Scheme for Masking Output of Scan Chains in Test Circuit 审中-公开
标题翻译：测试电路中扫描链屏蔽输出方案
公开(公告)号：US20160341795A1
公开(公告)日：2016-11-24
申请号：US15230860
申请日：2016-08-08
申请人： Synopsys, Inc.
发明人： Anshuman Chandra , Subramanian B. Chebiyam , Jyotirmoy Saikia , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3177 , G01R31/317
摘要： Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.
摘要翻译：操作集成电路的测试电路的扫描链，以将压缩机单个扇出或多个扇出。测试电路接收用于配置扫描链的扇出的扇出控制信号。如果扇出控制信号指示使用单扇区配置扫描链，则将扫描链的输出发送到压缩器的一个输入。如果扇出控制信号指示以多扇出配置扫描链，则将扫描链的输出发送到压缩机的多个输入。

4. 发明授权

US10605863B2 Mapping physical shift failures to scan cells for detecting physical faults in integrated circuits 有权
公开(公告)号：US10605863B2
公开(公告)日：2020-03-31
申请号：US15796423
申请日：2017-10-27
申请人： Synopsys, Inc.
发明人： Subhadip Kundu , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/3183 , G06F17/50
摘要： Information is received describing test response signals generated by scan cells of an integrated circuit and physical shift failures representing mismatches between the test response signals and expected test response signals of the integrated circuit. The test response signals are mapped to a subset of the scan cells associated with the physical shift failures. Fault simulation is performed for the mapped subset of the scan cells to identify physical faults located within the integrated circuit causing the physical shift failures.

5. 发明授权

US10067187B2 Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment 有权
公开(公告)号：US10067187B2
公开(公告)日：2018-09-04
申请号：US14335720
申请日：2014-07-18
申请人： Synopsys, Inc.
发明人： Anshuman Chandra , Subramanian Chebiyam , Jyotirmoy Saikia , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3185
摘要： A method for masking scan chains in a test circuit of an integrated circuit is disclosed. The test circuit includes multiple mask banks. Different mask patterns are stored in each of the mask banks. A first mask bank of the multiple mask banks is selected and the mask pattern stored in the selected first mask bank is used for masking the output of the scan chains of the test circuit during a first portion of a test cycle. A second mask bank of the multiple mask banks is selected and the ask pattern stored in the selected second mask bank is used for masking the output of the scan chains of the test circuit during a second portion of the test cycle.

6. 发明授权

US09417287B2 Scheme for masking output of scan chains in test circuit 有权
标题翻译：用于屏蔽测试电路中扫描链输出的方案
公开(公告)号：US09417287B2
公开(公告)日：2016-08-16
申请号：US14254423
申请日：2014-04-16
申请人： Synopsys, Inc.
发明人： Anshuman Chandra , Subramanian B. Chebiyam , Jyotirmoy Saikia , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3185 , G01R31/3177 , G06F11/27 , G01R31/3187
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/3185 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318566 , G01R31/3187 , G06F11/27
摘要： Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.
摘要翻译：操作集成电路的测试电路的扫描链，以将压缩机单个扇出或多个扇出。测试电路接收用于配置扫描链的扇出的扇出控制信号。如果扇出控制信号指示使用单扇区配置扫描链，则将扫描链的输出发送到压缩器的一个输入。如果扇出控制信号指示以多扇出配置扫描链，则将扫描链的输出发送到压缩机的多个输入。

7. 发明授权

US09329235B2 Localizing fault flop in circuit by using modified test pattern 有权
标题翻译：通过使用修改的测试图案来定位电路中的故障翻转
公开(公告)号：US09329235B2
公开(公告)日：2016-05-03
申请号：US14207070
申请日：2014-03-12
申请人： Synopsys, Inc.
发明人： Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3183 , G01R31/3181 , G01R31/319
CPC分类号： G01R31/318569 , G01R31/31813 , G01R31/318371 , G01R31/318544 , G01R31/31921
摘要： A method for localizing at least one scan flop associated with a fault in an integrated circuit. A first test pattern, including a first scan-in data and first control data, is generated. Based on the first control data of the first test pattern, a first fault data is generated by applying the first scan-in data of the first test pattern to scan flops in a test circuit of the integrated circuit. If the first fault data indicates that a fault may be present in the integrated circuit, a second test pattern, including a second scan-in data and a second control data is generated.
摘要翻译：一种用于定位与集成电路中的故障相关联的至少一个扫描触发器的方法。产生包括第一扫描数据和第一控制数据的第一测试图案。基于第一测试图案的第一控制数据，通过将第一测试图案的第一扫描数据应用于集成电路的测试电路中的扫描器来产生第一故障数据。如果第一故障数据指示集成电路中可能存在故障，则生成包括第二扫描数据和第二控制数据的第二测试模式。

8. 发明申请

US20140317463A1 Scheme for Masking Output of Scan Chains in Test Circuit 有权
标题翻译：测试电路中扫描链屏蔽输出方案
公开(公告)号：US20140317463A1
公开(公告)日：2014-10-23
申请号：US14254423
申请日：2014-04-16
申请人： Synopsys, Inc.
发明人： Anshuman Chandra , Subramanian B. Chebiyam , Jyotirmoy Saikia , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/3185 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318566 , G01R31/3187 , G06F11/27
摘要： Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.
摘要翻译：操作集成电路的测试电路的扫描链，以将压缩机单个扇出或多个扇出。测试电路接收用于配置扫描链的扇出的扇出控制信号。如果扇出控制信号指示使用单扇区配置扫描链，则将扫描链的输出发送到压缩器的一个输入。如果扇出控制信号指示以多扇出配置扫描链，则将扫描链的输出发送到压缩机的多个输入。

9. 发明申请

US20180267098A1 MAPPING PHYSICAL SHIFT FAILURES TO SCAN CELLS FOR DETECTING PHYSICAL FAULTS IN INTEGRATED CIRCUITS 审中-公开
公开(公告)号：US20180267098A1
公开(公告)日：2018-09-20
申请号：US15796423
申请日：2017-10-27
申请人： Synopsys, Inc.
发明人： Subhadip Kundu , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3177
摘要： Information is received describing test response signals generated by scan cells of an integrated circuit and physical shift failures representing mismatches between the test response signals and expected test response signals of the integrated circuit. The test response signals are mapped to a subset of the scan cells associated with the physical shift failures. Fault simulation is performed for the mapped subset of the scan cells to identify physical faults located within the integrated circuit causing the physical shift failures.

10. 发明申请

US20170059651A1 IDENTIFYING FAILURE INDICATING SCAN TEST CELLS OF A CIRCUIT-UNDER-TEST 有权
标题翻译：识别电路故障的扫描测试电池的故障
公开(公告)号：US20170059651A1
公开(公告)日：2017-03-02
申请号：US14835650
申请日：2015-08-25
申请人： Synopsys, Inc.
发明人： Subhadip Kundu , Parthajit Bhattacharya , Rohit Kapur
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/318566 , G01R31/318547
摘要： A disclosed configuration is for identifying at least one failure indicating scan test cell of a circuit-under-test, CUT, the CUT having a plurality of scan test cells, is provided. The configuration comprises generating a plurality of error signatures by means of a compactor of the CUT, wherein each of the error signatures of the plurality of error signatures consist of a respective sequence of bits comprising at least one failure indicating bit, assigning each error signature to at least a first, a second and a third signature type according to a total number of failure indicating bits of the respective error signature and mapping at least a predefined minimum number of error signatures to respective scan test cells of the plurality of scan test cells. For each error signature, a priority of the mapping is determined by the signature type the respective error signature has been assigned to.
摘要翻译：所公开的配置用于识别至少一个故障指示被测电路CUT的扫描测试单元，具有多个扫描测试单元的CUT。该配置包括通过CUT的压缩器生成多个错误签名，其中多个错误签名的每个错误签名由包括至少一个故障指示位的相应的位序列组成，将每个错误签名分配给至少第一，第二和第三签名类型，根据指示相应错误签名的比特的故障总数，并将至少预定义的最小数量的错误签名映射到多个扫描测试单元中的各个扫描测试单元。对于每个错误签名，映射的优先级由相应错误签名已被分配给的签名类型来确定。

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