专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06756843B2 Signal transmitter with pulse-controlled amplification 有权
标题翻译：带脉冲控制放大的信号发射器
公开(公告)号：US06756843B2
公开(公告)日：2004-06-29
申请号：US10083439
申请日：2001-10-22
申请人： Sylvain Charley , Emmanuel Savin
发明人： Sylvain Charley , Emmanuel Savin
IPC分类号： H03F114
CPC分类号： H04B1/04 , H04B1/406
摘要： A transmitter of radioelectric signals includes a plurality of amplifiers PA1, PA2 for amplifying a signal Sin whose frequency is included in a predetermined frequency band, said signal Sin alternately carrying information and being in the quiescent state during first and second predetermined periods of time. The transmitter additionally includes a detector DET intended to supply a detection signal AP having active states and inactive states during the first and the second predetermined periods of time, respectively, and a controller CNT intended to supply signals S1 and S2, when the detection signal AP is in the active state, which signals are used to inhibit the amplifiers which are not optimized for the frequency band wherein the frequency of the signal Sin to be amplified is included.
摘要翻译：放大电信号的发射机包括多个放大器PA1，PA2，用于放大频率包含在预定频带中的信号Sin，所述信号Sin交替地携带信息并在第一和第二预定时段期间处于静止状态。发射机还包括检测器DET，其用于分别在第一和第二预定时段期间提供具有活动状态和无效状态的检测信号AP，以及用于在检测信号AP 处于活动状态，哪些信号被用于抑制未被包括要被放大的信号Sin的频率的频带未优化的放大器。

2. 发明授权

US08184415B2 ESD-protection device, a semiconductor device and integrated system in a package comprising such a device 有权
标题翻译： ESD保护装置，包括这种装置的封装中的半导体装置和集成系统
公开(公告)号：US08184415B2
公开(公告)日：2012-05-22
申请号：US12525179
申请日：2008-02-08
申请人： Emmanuel Savin , Stephane Bouvier
发明人： Emmanuel Savin , Stephane Bouvier
IPC分类号： H02H3/22
CPC分类号： H01L27/0255 , H01L29/861
摘要： The invention relates to an ESD protection device comprising: a first contact (10) and a second contact (20), and an electrical node (12); a bipolar transistor (6) having a base, an emitter, and a collector, the base and emitter forming a base-emitter junction, the base and collector forming a base-collector junction, the emitter being connected to the first contact (10), the collector being connected to the second contact (20), the base being connect to the electrical node (12); a first diode (1) connected between the electrical node (12) and the first contact (10), the first diode (1) comprising a first junction arranged in the same direction as the base-emitter junction, and—a second diode (2) connected between the electrical node (12) and the second contact (20), in anti-series with the first diode (1) on a path from the first contact (10) to the second contact (20), the second diode (2) comprising a second junction arranged in the same direction as the base-collector junction, wherein the bipolar transistor (6) is dimensioned to have such a current gain (β) that the voltage-current characteristic of the ESD protection device, measured between the first (10) and second contact (20), exhibits a voltage snap-back effect (SNP) at its trigger voltage (Vtrig). The voltage snap-back effect (SNP) results in a lower clamping voltage of the ESD protection device. The invention further relates a semiconductor device and an integrated system in a package comprising said ESD protection device.
摘要翻译：本发明涉及ESD保护装置，其包括：第一触点（10）和第二触点（20）以及电节点（12）; 具有基极，发射极和集电极的双极晶体管（6），所述基极和发射极形成基极 - 发射极结，所述基极和集电极形成基极 - 集电极结，所述发射极连接到所述第一触点（10）所述集电器连接到所述第二触点（20），所述基座连接到所述电节点（12）; 连接在电节点（12）和第一触点（10）之间的第一二极管（1），第一二极管（1）包括沿与基极 - 发射极结方向相同的方向布置的第一结和第二二极管 2）连接在电节点（12）和第二触点（20）之间，在从第一触点（10）到第二触点（20）的路径上与第一二极管（1）反串联，第二二极管（2）包括沿与所述基极 - 集电极结相同的方向布置的第二结，其中所述双极晶体管（6）的尺寸被设计成具有所述ESD保护装置的电压 - 电流特性的电流增益（＆在第一触点（10）和第二触点（20）之间测量的触发电压（Vtrig）具有电压回复效应（SNP）。电压回复效应（SNP）导致ESD保护器件的钳位电压较低。本发明还涉及一种包括所述ESD保护装置的封装中的半导体器件和集成系统。

3. 发明申请

US20100085672A1 ESD-PROTECTION DEVICE, A SEMICONDUCTOR DEVICE AND INTEGRATED SYSTEM IN A PACKAGE COMPRISING SUCH A DEVICE 有权
标题翻译： ESD保护装置，包含这种装置的包装中的半导体装置和集成系统
公开(公告)号：US20100085672A1
公开(公告)日：2010-04-08
申请号：US12525179
申请日：2008-02-08
申请人： Emmanuel Savin , Stephane Bouvier
发明人： Emmanuel Savin , Stephane Bouvier
IPC分类号： H02H9/00
CPC分类号： H01L27/0255 , H01L29/861
摘要： The invention relates to an ESD protection device comprising: a first contact (10) and a second contact (20), and an electrical node (12); a bipolar transistor (6) having a base, an emitter, and a collector, the base and emitter forming a base-emitter junction, the base and collector forming a base-collector junction, the emitter being connected to the first contact (10), the collector being connected to the second contact (20), the base being connect to the electrical node (12); a first diode (1) connected between the electrical node (12) and the first contact (10), the first diode (1) comprising a first junction arranged in the same direction as the base-emitter junction, and—a second diode (2) connected between the electrical node (12) and the second contact (20), in anti-series with the first diode (1) on a path from the first contact (10) to the second contact (20), the second diode (2) comprising a second junction arranged in the same direction as the base-collector junction, wherein the bipolar transistor (6) is dimensioned to have such a current gain (β) that the voltage-current characteristic of the ESD protection device, measured between the first (10) and second contact (20), exhibits a voltage snap-back effect (SNP) at its trigger voltage (Vtrig). The voltage snap-back effect (SNP) results in a lower clamping voltage of the ESD protection device. The invention further relates a semiconductor device and an integrated system in a package comprising said ESD protection device.
摘要翻译：本发明涉及ESD保护装置，其包括：第一触点（10）和第二触点（20）以及电节点（12）; 具有基极，发射极和集电极的双极晶体管（6），所述基极和发射极形成基极 - 发射极结，所述基极和集电极形成基极 - 集电极结，所述发射极连接到所述第一触点（10）所述集电器连接到所述第二触点（20），所述基座连接到所述电节点（12）; 连接在电节点（12）和第一触点（10）之间的第一二极管（1），第一二极管（1）包括沿与基极 - 发射极结方向相同的方向布置的第一结和第二二极管 2）连接在电节点（12）和第二触点（20）之间，在从第一触点（10）到第二触点（20）的路径上与第一二极管（1）反串联，第二二极管（2）包括沿与所述基极 - 集电极结相同的方向布置的第二结，其中所述双极晶体管（6）的尺寸被设计成具有所述ESD保护装置的电压 - 电流特性的电流增益（＆在第一触点（10）和第二触点（20）之间测量的触发电压（Vtrig）具有电压回复效应（SNP）。电压回复效应（SNP）导致ESD保护器件的钳位电压较低。本发明还涉及一种包括所述ESD保护装置的封装中的半导体器件和集成系统。

4. 发明授权

US07126364B2 Interface comprising a thin PCB with protrusions for testing an integrated circuit 有权
标题翻译：接口包括具有用于测试集成电路的突起的薄PCB
公开(公告)号：US07126364B2
公开(公告)日：2006-10-24
申请号：US10527108
申请日：2003-09-04
申请人： Frédéric Jardin-Lemagnen , Emmanuel Savin , Sébastien Leruez
发明人： Frédéric Jardin-Lemagnen , Emmanuel Savin , Sébastien Leruez
IPC分类号： G01R31/02
CPC分类号： G01R1/0408 , G01R1/045 , G01R1/0466 , G01R1/07378
摘要： The invention relates to a test device for testing an integrated circuit called test circuit, comprising a plurality of housings intended to be tested in a printed circuit called main circuit. The device comprises an insulating membrane of soft material having two opposite surfaces covered by two conductive layers interconnected by via holes and intended to be in contact with the test circuit and the main circuit respectively, under the influence of a pressure exerted during the test between the test circuit and the main circuit pressing the test device. Protrusions are arranged on at least one of the two layers in a predefined pattern as a function of said pins, tabs, pads etc. of the test circuit so as to ensure a contact quality between said layer and the circuit (to be tested or the main circuit) having contact with said layer under the influence of said pressing action.
摘要翻译：本发明涉及一种用于测试称为测试电路的集成电路的测试装置，包括多个用于在被称为主电路的印刷电路中测试的外壳。该装置包括一个软质材料的绝缘膜，两个相对的表面被两个导电层覆盖，两个导电层由通孔互连，并分别在测试电路和主电路之间施加的压力测试电路和主电路按下测试设备。作为测试电路的所述引脚，突片，焊盘等的函数，以预定模式将突出部布置在两层中的至少一个上，以确保所述层和电路之间的接触质量（待测试或主电路）在所述按压动作的影响下与所述层接触。

5. 发明授权

US08541865B2 Semiconductor device with improved ESD protection 有权
标题翻译：具有改进的ESD保护的半导体器件
公开(公告)号：US08541865B2
公开(公告)日：2013-09-24
申请号：US12739333
申请日：2008-10-22
申请人： Jean-Marc Yannou , Johannes Van Zwol , Emmanuel Savin
发明人： Jean-Marc Yannou , Johannes Van Zwol , Emmanuel Savin
IPC分类号： H01L29/866 , H01L21/762
CPC分类号： H01L23/60 , H01L23/481 , H01L25/167 , H01L27/0255 , H01L27/0814 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/13024 , H01L2224/131 , H01L2924/3011 , H01L2924/00014
摘要： The present invention relates to a semiconductor device, comprising a semiconductor substrate (102) with a thickness of less than 100 micrometer and with a first substrate side and an opposite second substrate side. A plurality of at least four monolithically integrated Zener or avalanche diodes (164,166,168,170) with a reverse breakdown voltage of less than 20 V are defined in the semiconductor substrate and connected with each other in a series connection. The diodes are defined in a plurality of mutually isolated substrate islands (120,122,124,126) in the semiconductor substrate, at least one diode per substrate island. The substrate islands are laterally surrounded by through-substrate isolations extending from the first to the second substrate side and comprising a filling (128) that electrically isolates a respective substrate island from a respective laterally surrounding area of the semiconductor substrate.
摘要翻译：本发明涉及一种半导体器件，包括厚度小于100微米的半导体衬底（102），并具有第一衬底侧和相对的第二衬底侧。多个至少四个具有小于20V的反向击穿电压的齐纳二极管或雪崩二极管（164,166,168,170）被限定在半导体衬底中并以串联方式彼此连接。二极管限定在半导体衬底中的多个相互隔离的衬底岛（120,122,124,126）中，每个衬底岛至少有一个二极管。衬底岛被从第一衬底侧延伸到第二衬底侧的贯穿衬底隔离件横向包围，并且包括将相应衬底岛与半导体衬底的相应横向周围区域电隔离的填充物（128）。

6. 发明申请

US20110121425A1 SEMICONDUCTOR DEVICE WITH IMPROVED ESD PROTECTION 有权
标题翻译：具有改进的ESD保护的半导体器件
公开(公告)号：US20110121425A1
公开(公告)日：2011-05-26
申请号：US12739333
申请日：2008-10-22
申请人： Jean-Marc Yannou , Johannes Van Zwol , Emmanuel Savin
发明人： Jean-Marc Yannou , Johannes Van Zwol , Emmanuel Savin
IPC分类号： H01L29/866 , H01L21/762
CPC分类号： H01L23/60 , H01L23/481 , H01L25/167 , H01L27/0255 , H01L27/0814 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/13024 , H01L2224/131 , H01L2924/3011 , H01L2924/00014
摘要： The present invention relates to a semiconductor device, comprising a semiconductor substrate (102) with a thickness of less than 100 micrometer and with a first substrate side and an opposite second substrate side. A plurality of at least four monolithically integrated Zener or avalanche diodes (164,166,168,170) with a reverse breakdown voltage of less than 20 V are defined in the semiconductor substrate and connected with each other in a series connection. The diodes are defined in a plurality of mutually isolated substrate islands (120,122,124,126) in the semiconductor substrate, at least one diode per substrate island. The substrate islands are laterally surrounded by through-substrate isolations extending from the first to the second substrate side and comprising a filling (128) that electrically isolates a respective substrate island from a respective laterally surrounding area of the semiconductor substrate.
摘要翻译：本发明涉及一种半导体器件，包括厚度小于100微米的半导体衬底（102），并具有第一衬底侧和相对的第二衬底侧。多个至少四个具有小于20V的反向击穿电压的齐纳二极管或雪崩二极管（164,166,168,170）被限定在半导体衬底中并以串联方式彼此连接。二极管限定在半导体衬底中的多个相互隔离的衬底岛（120,122,124,126）中，每个衬底岛至少有一个二极管。衬底岛被从第一衬底侧延伸到第二衬底侧的贯穿衬底隔离件横向包围，并且包括将相应衬底岛与半导体衬底的相应横向周围区域电隔离的填充物（128）。

7. 发明申请

US20060033511A1 Interface comprising a thin pcb with protrusions for testing an integrated circuit 有权
标题翻译：接口包括具有用于测试集成电路的突起的薄pcb
公开(公告)号：US20060033511A1
公开(公告)日：2006-02-16
申请号：US10527108
申请日：2003-09-04
申请人： Frederic Jardin-Lemagnen , Emmanuel Savin , Sebastien Leruez
发明人： Frederic Jardin-Lemagnen , Emmanuel Savin , Sebastien Leruez
IPC分类号： G01R31/02
CPC分类号： G01R1/0408 , G01R1/045 , G01R1/0466 , G01R1/07378
摘要： The invention relates to a test device for testing an integrated circuit called circuit to be tested, comprising one of a plurality of housings in a printed circuit called main circuit. The device comprises an insulating membrane of soft material having two opposite surfaces covered by two conductive layers interconnected by via holes and intended to be in contact with the circuit to be tested and the main circuit respectively, under the influence of a pressure exerted during the test. Protrusions are arranged on at least one of the two layers in a predefined pattern as a function of pins, tabs, pads etc. of the circuit to be tested so as to ensure a contact quality between said layer and the circuit (to be tested or the main circuit) having contact with said layer under the influence of said pressing action.
摘要翻译：本发明涉及一种用于测试称为被测电路的集成电路的测试装置，包括被称为主电路的印刷电路中的多个外壳之一。该装置包括一个软质材料的绝缘膜，两个相对的表面被两个导电层覆盖，两个导电层通过通孔互相连接，并且在试验过程中施加压力的影响下分别与被测试电路和主电路接触。作为待测电路的引脚，突片，焊盘等的函数，预定图案中的突起被布置在两层中的至少一层上，以确保所述层与电路之间的接触质量（待测试或所述主电路）在所述按压动作的影响下与所述层接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式