专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140191372A1 SPACER ASSISTED PITCH DIVISION LITHOGRAPHY 有权
标题翻译：间隔辅助切片分割图
公开(公告)号：US20140191372A1
公开(公告)日：2014-07-10
申请号：US13976077
申请日：2011-12-29
申请人： Swaminathan Sivakumar , Elliot N. Tan
发明人： Swaminathan Sivakumar , Elliot N. Tan
IPC分类号： H01L21/02 , H01L29/06
CPC分类号： H01L21/02587 , H01L21/02658 , H01L21/0337 , H01L21/28 , H01L21/76816 , H01L29/0684 , Y10S438/942
摘要： Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.
摘要翻译：公开了使用单个间隔物沉积来实现具有可变线宽度和可变空间宽度的间距的基于间隔物的间距光刻技术。所得到的特征间距可以处于或低于所使用的曝光系统的分辨率极限，但是它们不需要并且可以进一步减少（例如，减半），如所需的随后的间隔物形成和图案转移过程所需的多次这里。这种基于间隔物的螺距分割技术可以用于例如以比原始骨架图案小的间距来限定窄导电线，金属栅极和其它这样的小特征。

2. 发明授权

US08860184B2 Spacer assisted pitch division lithography 有权
标题翻译：间隔辅助间距光刻
公开(公告)号：US08860184B2
公开(公告)日：2014-10-14
申请号：US13976077
申请日：2011-12-29
申请人： Swaminathan Sivakumar , Elliot N. Tan
发明人： Swaminathan Sivakumar , Elliot N. Tan
IPC分类号： H01L29/06 , H01L23/58 , H01L21/44 , H01L21/02
CPC分类号： H01L21/02587 , H01L21/02658 , H01L21/0337 , H01L21/28 , H01L21/76816 , H01L29/0684 , Y10S438/942
摘要： Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.
摘要翻译：公开了使用单个间隔物沉积来实现具有可变线宽度和可变空间宽度的间距的基于间隔物的间距光刻技术。所得到的特征间距可以处于或低于所使用的曝光系统的分辨率极限，但是它们不需要并且可以进一步减少（例如，减半），如所需的随后的间隔物形成和图案转移过程所需的多次这里。这种基于间隔物的螺距分割技术可以用于例如以比原始骨架图案小的间距来限定窄导电线，金属栅极和其它这样的小特征。

3. 发明授权

US09558947B2 Pattern decomposition lithography techniques 有权
标题翻译：图案分解光刻技术
公开(公告)号：US09558947B2
公开(公告)日：2017-01-31
申请号：US13976082
申请日：2011-12-29
申请人： Charles H. Wallace , Hossam M. Abdallah , Elliot N. Tan , Swaminathan Sivakumar , Oleg Golonzka , Robert M. Bigwood
发明人： Charles H. Wallace , Hossam M. Abdallah , Elliot N. Tan , Swaminathan Sivakumar , Oleg Golonzka , Robert M. Bigwood
IPC分类号： H01L21/312 , H01L21/263 , H01L21/027 , G03F7/20 , H01L21/02 , H01L27/02 , G03F1/50 , G03F7/00 , G03F7/40
CPC分类号： H01L24/09 , G03F1/50 , G03F1/70 , G03F7/0035 , G03F7/16 , G03F7/40 , G03F7/70741 , H01L21/02345 , H01L21/0273 , H01L21/2633 , H01L21/30604 , H01L21/3086 , H01L27/0207 , H01L2224/0801 , H01L2224/08053 , H01L2224/0912 , H01L2924/14
摘要： Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may he arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.
摘要翻译：公开了用于通过将其分解（分解）成多个单向目标特征来实现二维目标光刻特征/图案的技术，其在聚合时基本上（例如，完全）代表原始目标特征而不留下未表示的余数（例如，全数量的单向目标特征）。单向目标特征可以任意分组，使得在分组内，所有单向目标特征共享共同的目标宽度值。在提供多个这样的分组的情况下，个体分组可以具有或可以不具有相同的共同目标宽度值。在一些情况下，提供一系列光罩，每个掩模版具有与单向目标特征的分组相关的掩模图案。基本上（例如，完全）通过聚集的标线系列曝光光致抗蚀剂材料产生原始目标特征/图案。图案分解技术可以集成到任何数量的图案化工艺中，例如光刻冷冻 - 光刻蚀刻和光蚀刻 - 光蚀刻图案化工艺。

4. 发明申请

US20140117488A1 PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES 有权
标题翻译：图案分解光刻技术
公开(公告)号：US20140117488A1
公开(公告)日：2014-05-01
申请号：US13976082
申请日：2011-12-29
申请人： Charles H. Wallace , Hossam M. Abdallah , Elliot N. Tan , Swaminathan Sivakumar , Oleg Golonzka , Robert M. Bigwood
发明人： Charles H. Wallace , Hossam M. Abdallah , Elliot N. Tan , Swaminathan Sivakumar , Oleg Golonzka , Robert M. Bigwood
IPC分类号： H01L21/263 , H01L27/02 , H01L21/02 , G03F7/20
CPC分类号： H01L24/09 , G03F1/50 , G03F1/70 , G03F7/0035 , G03F7/16 , G03F7/40 , G03F7/70741 , H01L21/02345 , H01L21/0273 , H01L21/2633 , H01L21/30604 , H01L21/3086 , H01L27/0207 , H01L2224/0801 , H01L2224/08053 , H01L2224/0912 , H01L2924/14
摘要： Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may he arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.
摘要翻译：公开了用于通过将其分解（分解）成多个单向目标特征来实现二维目标光刻特征/图案的技术，其在聚合时基本上（例如，完全）代表原始目标特征而不留下未表示的余数（例如，全数量的单向目标特征）。单向目标特征可以任意分组，使得在分组内，所有单向目标特征共享共同的目标宽度值。在提供多个这样的分组的情况下，个体分组可以具有或可以不具有相同的共同目标宽度值。在一些情况下，提供一系列光罩，每个掩模版具有与单向目标特征的分组相关的掩模图案。基本上（例如，完全）通过聚集的标线系列曝光光致抗蚀剂材料产生原始目标特征/图案。图案分解技术可以集成到任何数量的图案化工艺中，例如光刻冷冻 - 光刻蚀刻和光蚀刻 - 光蚀刻图案化工艺。

5. 发明授权

US08314034B2 Feature size reduction 有权
标题翻译：功能尺寸缩小
公开(公告)号：US08314034B2
公开(公告)日：2012-11-20
申请号：US12978160
申请日：2010-12-23
申请人： Elliot N. Tan , Michael K. Harper
发明人： Elliot N. Tan , Michael K. Harper
IPC分类号： H01L21/302
CPC分类号： H01L21/0337 , H01L21/0338
摘要： Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.
摘要翻译：提供了半导体器件制造方法。使用间隔件创建特征。方法包括产生由衬底表面上的至少两个第一特征构成的图案，在所述至少两个第一特征上沉积第一共形层，在第一共形层上沉积第二共形层，部分地去除第二共形层以部分曝光第一共形层，并且从第一特征和第二共形层之间部分地去除第一共形层，从而形成至少两个第二特征。可选地，在第二保形膜沉积之前，第一保形膜被部分地回蚀。

6. 发明申请

US20150214094A1 METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCONNECT STRUCTURES 有权
标题翻译：用于形成具有紧密间距互连结构的互连层的方法
公开(公告)号：US20150214094A1
公开(公告)日：2015-07-30
申请号：US14163323
申请日：2014-01-24
申请人： Christopher J. Jezewski , Jasmeet S. Chawla , Kanwal Jit Singh , Alan M. Myers , Elliot N. Tan , Richard E. Schenker
发明人： Christopher J. Jezewski , Jasmeet S. Chawla , Kanwal Jit Singh , Alan M. Myers , Elliot N. Tan , Richard E. Schenker
IPC分类号： H01L21/768
CPC分类号： H01L21/7688 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/76831 , H01L21/76886 , H01L21/76897 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to formed interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminated the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allows for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.
摘要翻译：用于形成在电介质层内具有紧密间距互连结构的互连层的工艺，其中用于形成的互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的电位。本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

7. 发明申请

US20120164837A1 FEATURE SIZE REDUCTION 有权
标题翻译：特征尺寸减少
公开(公告)号：US20120164837A1
公开(公告)日：2012-06-28
申请号：US12978160
申请日：2010-12-23
申请人： Elliot N. Tan , Michael K. Harper
发明人： Elliot N. Tan , Michael K. Harper
IPC分类号： H01L21/31
CPC分类号： H01L21/0337 , H01L21/0338
摘要： Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.
摘要翻译：提供了半导体器件制造方法。使用间隔件创建特征。方法包括产生由衬底表面上的至少两个第一特征构成的图案，在所述至少两个第一特征上沉积第一共形层，在第一共形层上沉积第二共形层，部分地去除第二共形层以部分曝光第一共形层，并且从第一特征和第二共形层之间部分地去除第一共形层，从而形成至少两个第二特征。可选地，在第二保形膜沉积之前，第一保形膜被部分地回蚀。

8. 发明授权

US10211088B2 Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects 有权
公开(公告)号：US10211088B2
公开(公告)日：2019-02-19
申请号：US15743616
申请日：2015-09-10
申请人： INTEL CORPORATION , Charles H. Wallace , Swaminathan Sivakumar
发明人： Charles H. Wallace , Elliot N. Tan , Paul A. Nyhus , Swaminathan Sivakumar
IPC分类号： H01L21/768 , H01L23/522 , H01L21/311 , H01L23/528 , H01L21/033
摘要： Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式