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1. 发明授权

US06187632B1 Anneal technique for reducing amount of electronic trap in gate oxide film of transistor 失效
标题翻译：减少晶体管栅极氧化膜中电子陷阱量的退火技术
公开(公告)号：US06187632B1
公开(公告)日：2001-02-13
申请号：US08994134
申请日：1997-12-19
申请人： Susumu Shuto , Miwa Tanaka , Masahisa Sonoda , Toshiaki Idaka , Kenichi Sasaki , Seiichi Mori
发明人： Susumu Shuto , Miwa Tanaka , Masahisa Sonoda , Toshiaki Idaka , Kenichi Sasaki , Seiichi Mori
IPC分类号： H01L2166
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/51 , Y10S438/902 , Y10S438/904
摘要： A memory cell of EEPROM having a floating gate, a control gate, a drain region, and a source region is formed on a silicon substrate. Thereafter, a BPSG film (interlayer insulating film) covering the memory cell is formed by CVD. After a wire including a bit line, an SiON film (passivation film), covering the silicon substrate and serving as an uppermost layer, is formed on an upper portion of the silicon substrate. Thereafter, annealing is performed to discharge water in the BPSG film to an outer portion of an LSI. The annealing is performed under a condition satisfying the following equation of t≧7.86×10−11×L2×exp (9115/T) where t is anneal time (minutes), L is a thickness (nm) of the passivation film, and T is anneal temperature (absolute temperature). Thereby, an amount of electronic trap in a gate oxide film of the transistor can be reduced.
摘要翻译：在硅衬底上形成具有浮置栅极，控制栅极，漏极区域和源极区域的EEPROM的存储单元。此后，通过CVD形成覆盖存储单元的BPSG膜（层间绝缘膜）。在包括位线的线之后，在硅衬底的上部形成覆盖硅衬底并用作最上层的SiON膜（钝化膜）。此后，进行退火以将BPSG膜中的水排出到LSI的外部。退火在满足以下等式的条件下进行，其中t为退火时间（分钟），L为钝化膜的厚度（nm），T为退火温度（绝对温度）。由此，可以减少晶体管的栅极氧化膜中的电子阱的量。

2. 发明授权

US6100579A Insulating film for use in semiconductor device 失效
标题翻译：绝缘膜用于半导体器件
公开(公告)号：US6100579A
公开(公告)日：2000-08-08
申请号：US983010
申请日：1998-07-02
申请人： Masahisa Sonoda , Susumu Shuto , Miwa Tanaka , Toshiaki Idaka , Hiroaki Tsunoda , Hitoshi Araki
发明人： Masahisa Sonoda , Susumu Shuto , Miwa Tanaka , Toshiaki Idaka , Hiroaki Tsunoda , Hitoshi Araki
IPC分类号： H01L21/8247 , H01L21/316 , H01L21/318 , H01L21/768 , H01L21/8242 , H01L23/00 , H01L23/29 , H01L23/522 , H01L23/532 , H01L27/108 , H01L29/78 , H01L29/788 , H01L29/792 , H01L23/58 , H01L21/469
CPC分类号： H01L23/291 , H01L23/5329 , H01L23/564 , H01L27/10844 , H01L2924/0002
摘要： In manufacturing a CVD film (interlayer insulating film or passivation film) using material gases containing a gas having Si--H combination, the amount of Si--H combination in the CVD film (12, 31, 32, 33, 34, 47, 48, 49, 57, 59) is set to 0.6.times.10.sup.21 cm.sup.-3 or less to thereby suppress the formation of electron traps in the gate oxide film or tunnel oxide film and prevent variations in the threshold of transistors. In addition, the moisture resistance can be improved by setting the refractive index of the CVD film to 1.65 or more or by setting the concentration of nitrogen in the CVD film to 3.times.10.sup.21 cm.sup.-3 or more.
摘要翻译： PCT No.PCT / JP97 / 01378 Sec。 371日期：1998年7月2日 102（e）日期1998年7月2日PCT 1997年4月22日PCT PCT。公开号WO97 / 40533 日期1997年10月30日在使用含有Si-H组合气体的原料气体制造CVD膜（层间绝缘膜或钝化膜）时，CVD膜中的Si-H组合量（12,31,32,33， 34,47,48,49,57,59）设定为0.6×10 21 cm -3以下，从而抑制栅极氧化膜或隧道氧化物膜中的电子陷阱的形成，并防止晶体管的阈值的变化。此外，通过将CVD膜的折射率设定为1.65以上或通过将CVD膜中的氮浓度设定为3×10 21 cm -3以上，可以提高耐湿性。

3. 发明申请

US20060081907A1 Nonvolatile semiconductor memory device having grooves isolating the floating electrodes of memory cells and method of manufacturing the nonvolatile semiconductor memory device 审中-公开
公开(公告)号：US20060081907A1
公开(公告)日：2006-04-20
申请号：US11290461
申请日：2005-12-01
申请人： Masahisa Sonoda , Hiroaki Tsunoda , Seiichi Mori
发明人： Masahisa Sonoda , Hiroaki Tsunoda , Seiichi Mori
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A plurality of nonvolatile memory elements formed on element regions respectively isolated by element isolation regions on a main surface of a first conductive type semiconductor substrate, the nonvolatile semiconductor memory elements comprising a gate insulating film formed on the main surface of the semiconductor substrate, a plurality of floating electrodes formed along a first direction on the gate insulating film, a plurality of grooves formed among the plurality of floating electrodes, groove insulating films filled in the plurality of the grooves, a second conductive type impurity diffusion region formed along a second direction so as to sandwich the floating electrodes, interelectrode insulating films formed along the first direction on the plurality of floating electrodes and the groove insulating films, and control electrodes formed on the interelectrode insulating films.

4. 发明授权

US07557401B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07557401B2
公开(公告)日：2009-07-07
申请号：US11405538
申请日：2006-04-18
申请人： Keisuke Yonehama , Seiichi Mori , Eiji Sakagami , Masahisa Sonoda
发明人： Keisuke Yonehama , Seiichi Mori , Eiji Sakagami , Masahisa Sonoda
IPC分类号： H01L29/76
CPC分类号： H01L21/76897 , H01L21/28273 , H01L27/1052 , H01L27/115 , H01L27/11521
摘要： A semiconductor device includes an element isolation insulating film adjacent to an active area, a gate insulating film formed on a semiconductor substrate in the active area, paired gate electrodes located on the gate insulating film, a contact plug located on the active area between the gate electrodes, a pair of first upper lines located on the gate electrodes, a second upper line located on the gate electrodes, and a stopper film above upper surfaces of the gate electrodes and side surfaces of the gate electrodes. The element isolation insulating film has a first height of an upper surface thereof with reference to an upper surface of the semiconductor substrate and a second height of another upper surface thereof with reference to another upper surface of the semiconductor substrate. The first height is smaller than the second height.
摘要翻译：半导体器件包括与有源区相邻的元件隔离绝缘膜，形成在有源区中的半导体衬底上的栅极绝缘膜，位于栅极绝缘膜上的成对栅电极，位于栅极之间的有源区上的接触插塞电极，位于栅极电极上的一对第一上部线，位于栅电极上的第二上部线，以及栅电极的上表面和栅电极的侧表面之上的阻挡膜。元件隔离绝缘膜相对于半导体衬底的上表面具有上表面的第一高度，并且相对于半导体衬底的另一上表面具有另一上表面的第二高度。第一个高度小于第二个高度。

5. 发明申请

US20060234448A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060234448A1
公开(公告)日：2006-10-19
申请号：US11405538
申请日：2006-04-18
申请人： Keisuke Yonehama , Seiichi Mori , Eiji Sakagami , Masahisa Sonoda
发明人： Keisuke Yonehama , Seiichi Mori , Eiji Sakagami , Masahisa Sonoda
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/28273 , H01L27/1052 , H01L27/115 , H01L27/11521
摘要： A semiconductor device includes an element isolation insulating film, memory cell transistors formed in an element isolation region and having respective gate electrodes, and a stopper film for forming a contact, formed both on a sidewall of the gate electrode of each transistor and on the element isolation insulating film between the gate electrodes. A level difference is set between the upper surface of the element isolation insulating film and the upper surface of the semiconductor substrate in the element isolation region. The level difference is set so that a level difference between the gate electrodes is smaller than a level difference in the gate electrode. Furthermore, the surface of the semiconductor substrate in the drain contact formation region is located lower than the surface of the semiconductor substrate corresponding to the gate electrode.
摘要翻译：半导体器件包括元件隔离绝缘膜，形成在元件隔离区中并具有各自的栅电极的存储单元晶体管，以及形成接触的阻挡膜，形成在每个晶体管的栅电极的侧壁和元件上隔离绝缘膜之间的栅电极。在元件隔离绝缘膜的上表面和元件隔离区域中的半导体衬底的上表面之间设置有电平差。电平差被设定为使得栅电极之间的电平差小于栅电极中的电平差。此外，漏极接触形成区域中的半导体衬底的表面位于比对应于栅电极的半导体衬底的表面更低的位置。

6. 发明授权

US07026683B2 Nonvolatile semiconductor memory device having grooves isolating the floating electrodes of memory cells and method of manufacturing the nonvolatile semiconductor memory device 失效
标题翻译：具有隔离存储单元的浮置电极的槽的非易失性半导体存储器件以及制造非易失性半导体存储器件的方法
公开(公告)号：US07026683B2
公开(公告)日：2006-04-11
申请号：US10642666
申请日：2003-08-19
申请人： Masahisa Sonoda , Hiroaki Tsunoda , Seiichi Mori
发明人： Masahisa Sonoda , Hiroaki Tsunoda , Seiichi Mori
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A plurality of nonvolatile memory elements formed on element regions respectively isolated by element isolation regions on a main surface of a first conductive type semiconductor substrate, the nonvolatile semiconductor memory elements comprising a gate insulating film formed on the main surface of the semiconductor substrate, a plurality of floating electrodes formed along a first direction on the gate insulating film, a plurality of grooves formed among the plurality of floating electrodes, groove insulating films filled in the plurality of the grooves, a second conductive type impurity diffusion region formed along a second direction so as to sandwich the floating electrodes, interelectrode insulating films formed along the first direction on the plurality of floating electrodes and the groove insulating films, and control electrodes formed on the interelectrode insulating films.
摘要翻译：多个非易失性存储元件，形成在由第一导电型半导体衬底的主表面上的元件隔离区分隔开的元件区域上，所述非易失性半导体存储元件包括形成在半导体衬底的主表面上的栅极绝缘膜，多个在所述栅极绝缘膜上沿着第一方向形成的浮置电极，在所述多个浮置电极之间形成的多个沟槽，填充在所述多个沟槽中的沟槽绝缘膜，沿着第二方向形成的第二导电型杂质扩散区域，夹着浮动电极，在多个浮置电极和沟槽绝缘膜上沿着第一方向形成的电极间绝缘膜，以及形成在电极间绝缘膜上的控制电极。

7. 发明申请

US20080090378A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080090378A1
公开(公告)日：2008-04-17
申请号：US11868164
申请日：2007-10-05
申请人： Hiroaki Tsunoda , Masahisa Sonoda
发明人： Hiroaki Tsunoda , Masahisa Sonoda
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L27/115 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： A method of fabricating a semiconductor device includes forming a trench in a semiconductor substrate by a reactive ion etching (RIE) method, the trench having an inner surface, treating the trench with diluted hydrofluoric acid, treating the interior of the trench by a hydrofluoric acid vapor phase cleaning (HFVPC) method, forming a high temperature oxide (HTO) film along the inner surface of the trench, and forming an element isolation insulating film inside the HTO film in the trench so that the trench is filled with the element isolation insulating film.
摘要翻译：制造半导体器件的方法包括通过反应离子蚀刻（RIE）法在半导体衬底中形成沟槽，沟槽具有内表面，用稀氢氟酸处理沟槽，用氢氟酸处理沟槽的内部气相清洗（HFVPC）方法，沿着沟槽的内表面形成高温氧化物（HTO）膜，并且在沟槽内的HTO膜内部形成元件隔离绝缘膜，使沟槽填充元件绝缘隔离层电影。

8. 发明申请

US20050116304A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050116304A1
公开(公告)日：2005-06-02
申请号：US11031044
申请日：2005-01-10
申请人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
发明人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L21/336
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.
摘要翻译：在包括多个元件区域的半导体器件和基于将元件区域彼此电隔离的STI（浅沟槽隔离）的元件隔离区域中，每个元件区域包括：一个通道区域形成为在水平方向夹着沟道区的源/漏区; 形成在通道区域上并且鸟嘴的角度为1度或更小的栅极绝缘膜，所述鸟喙从元件隔离区的与面向沟道区域的表面相对的表面形成，大致垂直于源极/漏极区域夹着沟道区域的方向的水平方向; 以及形成在栅极绝缘膜上的栅极电极层。

9. 发明授权

US07368342B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07368342B2
公开(公告)日：2008-05-06
申请号：US10948661
申请日：2004-09-24
申请人： Masahisa Sonoda , Hiroaki Tsunoda , Eiji Sakagami , Hidemi Kanetaka , Kenji Matsuzaki , Takanori Matsumoto
发明人： Masahisa Sonoda , Hiroaki Tsunoda , Eiji Sakagami , Hidemi Kanetaka , Kenji Matsuzaki , Takanori Matsumoto
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/76232 , H01L21/823481 , H01L21/823878
摘要： A method for manufacturing a semiconductor device includes forming a gate-insulating film on a semiconductor substrate; forming a gate electrode on the gate-insulating film to be electrically insulated from the semiconductor substrate; etching the gate electrode, the gate insulating film and the semiconductor substrate to form a trench which is used to electrically isolate a device region for forming a device from the remainder region on the substrate top surface; and etching the inside of the trench using a gas containing Cl2 and HBr with a different condition from the etching condition of the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成栅极绝缘膜; 在所述栅极绝缘膜上形成与所述半导体衬底电绝缘的栅电极; 蚀刻栅电极，栅极绝缘膜和半导体衬底以形成用于将用于形成器件的器件区域与衬底顶表面上的其余区域电隔离的沟槽; 并使用与半导体衬底的蚀刻条件不同的条件，使用含有Cl 2 2和HBr的气体来蚀刻沟槽的内部。

10. 发明授权

US06984858B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06984858B2
公开(公告)日：2006-01-10
申请号：US10293254
申请日：2002-11-14
申请人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
发明人： Masahisa Sonoda , Tadashi Iguchi , Hiroaki Tsunoda , Eiji Sakagami
IPC分类号： H01L27/108
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823462
摘要： In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.
摘要翻译：在包括多个元件区域的半导体器件和基于将元件区域彼此电隔离的STI（浅沟槽隔离）的元件隔离区域中，每个元件区域包括：一个通道区域形成为在水平方向夹着沟道区的源/漏区; 形成在通道区域上并且鸟嘴的角度为1度或更小的栅极绝缘膜，所述鸟喙从元件隔离区的与面向沟道区域的表面相对的表面形成，大致垂直于源极/漏极区域夹着沟道区域的方向的水平方向; 以及形成在栅极绝缘膜上的栅极电极层。

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