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1. 发明授权

US6100579A Insulating film for use in semiconductor device 失效
标题翻译：绝缘膜用于半导体器件
公开(公告)号：US6100579A
公开(公告)日：2000-08-08
申请号：US983010
申请日：1998-07-02
申请人： Masahisa Sonoda , Susumu Shuto , Miwa Tanaka , Toshiaki Idaka , Hiroaki Tsunoda , Hitoshi Araki
发明人： Masahisa Sonoda , Susumu Shuto , Miwa Tanaka , Toshiaki Idaka , Hiroaki Tsunoda , Hitoshi Araki
IPC分类号： H01L21/8247 , H01L21/316 , H01L21/318 , H01L21/768 , H01L21/8242 , H01L23/00 , H01L23/29 , H01L23/522 , H01L23/532 , H01L27/108 , H01L29/78 , H01L29/788 , H01L29/792 , H01L23/58 , H01L21/469
CPC分类号： H01L23/291 , H01L23/5329 , H01L23/564 , H01L27/10844 , H01L2924/0002
摘要： In manufacturing a CVD film (interlayer insulating film or passivation film) using material gases containing a gas having Si--H combination, the amount of Si--H combination in the CVD film (12, 31, 32, 33, 34, 47, 48, 49, 57, 59) is set to 0.6.times.10.sup.21 cm.sup.-3 or less to thereby suppress the formation of electron traps in the gate oxide film or tunnel oxide film and prevent variations in the threshold of transistors. In addition, the moisture resistance can be improved by setting the refractive index of the CVD film to 1.65 or more or by setting the concentration of nitrogen in the CVD film to 3.times.10.sup.21 cm.sup.-3 or more.
摘要翻译： PCT No.PCT / JP97 / 01378 Sec。 371日期：1998年7月2日 102（e）日期1998年7月2日PCT 1997年4月22日PCT PCT。公开号WO97 / 40533 日期1997年10月30日在使用含有Si-H组合气体的原料气体制造CVD膜（层间绝缘膜或钝化膜）时，CVD膜中的Si-H组合量（12,31,32,33， 34,47,48,49,57,59）设定为0.6×10 21 cm -3以下，从而抑制栅极氧化膜或隧道氧化物膜中的电子陷阱的形成，并防止晶体管的阈值的变化。此外，通过将CVD膜的折射率设定为1.65以上或通过将CVD膜中的氮浓度设定为3×10 21 cm -3以上，可以提高耐湿性。

2. 发明授权

US06187632B1 Anneal technique for reducing amount of electronic trap in gate oxide film of transistor 失效
标题翻译：减少晶体管栅极氧化膜中电子陷阱量的退火技术
公开(公告)号：US06187632B1
公开(公告)日：2001-02-13
申请号：US08994134
申请日：1997-12-19
申请人： Susumu Shuto , Miwa Tanaka , Masahisa Sonoda , Toshiaki Idaka , Kenichi Sasaki , Seiichi Mori
发明人： Susumu Shuto , Miwa Tanaka , Masahisa Sonoda , Toshiaki Idaka , Kenichi Sasaki , Seiichi Mori
IPC分类号： H01L2166
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/51 , Y10S438/902 , Y10S438/904
摘要： A memory cell of EEPROM having a floating gate, a control gate, a drain region, and a source region is formed on a silicon substrate. Thereafter, a BPSG film (interlayer insulating film) covering the memory cell is formed by CVD. After a wire including a bit line, an SiON film (passivation film), covering the silicon substrate and serving as an uppermost layer, is formed on an upper portion of the silicon substrate. Thereafter, annealing is performed to discharge water in the BPSG film to an outer portion of an LSI. The annealing is performed under a condition satisfying the following equation of t≧7.86×10−11×L2×exp (9115/T) where t is anneal time (minutes), L is a thickness (nm) of the passivation film, and T is anneal temperature (absolute temperature). Thereby, an amount of electronic trap in a gate oxide film of the transistor can be reduced.
摘要翻译：在硅衬底上形成具有浮置栅极，控制栅极，漏极区域和源极区域的EEPROM的存储单元。此后，通过CVD形成覆盖存储单元的BPSG膜（层间绝缘膜）。在包括位线的线之后，在硅衬底的上部形成覆盖硅衬底并用作最上层的SiON膜（钝化膜）。此后，进行退火以将BPSG膜中的水排出到LSI的外部。退火在满足以下等式的条件下进行，其中t为退火时间（分钟），L为钝化膜的厚度（nm），T为退火温度（绝对温度）。由此，可以减少晶体管的栅极氧化膜中的电子阱的量。

3. 发明授权

US07803706B2 Semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US07803706B2
公开(公告)日：2010-09-28
申请号：US12408593
申请日：2009-03-20
申请人： Toshiaki Idaka , Kazuyuki Yahiro
发明人： Toshiaki Idaka , Kazuyuki Yahiro
IPC分类号： H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/3105 , H01L29/7843
摘要： Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.
摘要翻译：公开了一种半导体器件制造方法，其中形成氮化硅膜以覆盖形成在半导体衬底上的n沟道晶体管并且在沟道长度方向上施加拉应力到n沟道晶体管的沟道，该方法包括：在n沟道晶体管上形成第一层氮化硅膜; 用紫外线照射第一层氮化硅膜; 并且在紫外线照射之后，形成比第一层氮化硅膜上方的第一层氮化硅膜薄的至少一个氮化硅膜。通过各个步骤形成施加拉伸应力的氮化硅膜。

4. 发明授权

US07960764B2 Semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US07960764B2
公开(公告)日：2011-06-14
申请号：US12805940
申请日：2010-08-25
申请人： Toshiaki Idaka , Kazuyuki Yahiro
发明人： Toshiaki Idaka , Kazuyuki Yahiro
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L23/58
CPC分类号： H01L21/3105 , H01L29/7843
摘要： Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.
摘要翻译：公开了一种半导体器件制造方法，其中形成氮化硅膜以覆盖形成在半导体衬底上的n沟道晶体管并且在沟道长度方向上施加拉应力到n沟道晶体管的沟道，该方法包括：在n沟道晶体管上形成第一层氮化硅膜; 用紫外线照射第一层氮化硅膜; 并且在紫外线照射之后，形成比第一层氮化硅膜上方的第一层氮化硅膜薄的至少一个氮化硅膜。通过各个步骤形成施加拉伸应力的氮化硅膜。

5. 发明申请

US20100320512A1 Semiconductor device manufacturing method and semiconductor device 有权
公开(公告)号：US20100320512A1
公开(公告)日：2010-12-23
申请号：US12805940
申请日：2010-08-25
申请人： Toshiaki Idaka , Kazuyuki Yahiro
发明人： Toshiaki Idaka , Kazuyuki Yahiro
IPC分类号： H01L29/49
CPC分类号： H01L21/3105 , H01L29/7843
摘要： Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.

6. 发明授权

US07795142B2 Method for fabricating a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07795142B2
公开(公告)日：2010-09-14
申请号：US12370055
申请日：2009-02-12
申请人： Hideaki Masuda , Hideshi Miyajima , Toshiaki Idaka
发明人： Hideaki Masuda , Hideshi Miyajima , Toshiaki Idaka
IPC分类号： H01L21/44
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/3105 , H01L21/31116 , H01L21/76802 , H01L21/7682 , H01L21/76822 , H01L21/76825 , H01L21/76826 , H01L21/76835 , H01L2221/1047
摘要： A method for fabricating a semiconductor device includes forming a dielectric film containing a porogen material above a substrate; removing a portion of the porogen material contained in the dielectric film so as to make a concentration of the porogen material higher in a part on a lower side of the dielectric film than in another part on a higher side of the dielectric film; forming an opening halfway in the dielectric film from which a portion of the porogen material has been removed to leave the dielectric film below a bottom of the opening; removing or polymerizing a remainder of the porogen material contained in the dielectric film; and etching the bottom of the opening after removing or polymerizing the remainder of the porogen material.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成含有致孔剂材料的电介质膜; 去除电介质膜中包含的致孔剂材料的一部分，以使介电膜的下侧的一部分中的致孔剂材料的浓度高于在电介质膜的较高侧的另一部分的浓度; 在电介质膜的中间形成开口，其中一部分致孔剂材料从该绝缘膜被去除，以将电介质膜留在开口的底部以下; 去除或聚合包含在电介质膜中的致孔剂材料的剩余部分; 并且在除去或聚合剩余的致孔剂材料之后蚀刻开口的底部。

7. 发明授权

US5587337A Semiconductor process for forming bump electrodes with tapered sidewalls 失效
标题翻译：用于形成具有锥形侧壁的凸块电极的半导体工艺
公开(公告)号：US5587337A
公开(公告)日：1996-12-24
申请号：US444513
申请日：1995-05-19
申请人： Toshiaki Idaka , Hirokazu Ezawa
发明人： Toshiaki Idaka , Hirokazu Ezawa
IPC分类号： H01L21/3105 , H01L21/60 , H01L21/441
CPC分类号： H01L21/31058 , H01L24/11 , H01L2224/05556 , H01L2224/1147 , H01L2224/11472 , H01L2224/13016 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , Y10S438/948
摘要： A method of manufacturing bump electrodes with a larger top surface area than bottom surface area is disclosed. First, an organic layer is deposited. Then holes and grooves partially surrounding the holes are formed in the organic layer. Next, heat is applied to the organic film, causing the organic film to shrink. This causes the openings to expand at the top away from the grooves partially surrounding the holes. Metallic bumps are then deposited within the holes.
摘要翻译：公开了一种制造具有比底表面积更大的顶表面积的凸块电极的方法。首先，沉积有机层。然后在有机层中形成部分地围绕孔的孔和槽。接下来，对有机膜施加热量，导致有机膜收缩。这使得开口在顶部远离部分围绕孔的凹槽膨胀。然后将金属凸块沉积在孔内。

8. 发明授权

US5473197A Semiconductor device having bump electrodes with a trapezoidal cross-section along one axis 失效
标题翻译：半导体器件具有沿着一个轴线具有梯形横截面的凸起电极
公开(公告)号：US5473197A
公开(公告)日：1995-12-05
申请号：US246744
申请日：1994-05-20
申请人： Toshiaki Idaka , Hirokazu Ezawa
发明人： Toshiaki Idaka , Hirokazu Ezawa
IPC分类号： H01L21/3105 , H01L21/60 , H01L21/321 , H01L21/04
CPC分类号： H01L21/31058 , H01L24/11 , H01L2224/05556 , H01L2224/1147 , H01L2224/11472 , H01L2224/13016 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , Y10S438/948
摘要： Pads are formed on a semiconductor substrate and the pads are covered with a passivation film. Openings are formed in the passivation film and the pads are exposed via the openings. A barrier metal layer is formed on the bottom surface and side surface of each of the openings and the upper surface of the passivation film lying on the periphery of each of the openings. Bump electrodes are filled in the openings and project upwardly from the openings. The area of the upper surface of the bump electrode is larger than the area of the bottom surface thereof connected to the pad. The cross section of the bump electrode in a direction along the periphery of the semiconductor substrate takes a rectangular form and the cross section of the bump electrode in a direction perpendicular to the periphery of the semiconductor substrate takes a trapezium form having an upper side longer than a bottom side thereof.
摘要翻译：衬垫形成在半导体衬底上，衬垫被钝化膜覆盖。在钝化膜中形成开口，并且通过开口露出垫。在每个开口的底表面和侧表面以及位于每个开口的周边上的钝化膜的上表面形成阻挡金属层。凸起电极填充在开口中并从开口向上突出。突起电极的上表面的面积大于其与焊盘连接的底面的面积。突起电极的沿着半导体基板的周边的方向的截面呈矩形，并且突起电极在与半导体基板的周边垂直的方向上的横截面呈梯形，其上侧长于其底侧。

9. 发明授权

US4937652A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4937652A
公开(公告)日：1990-06-26
申请号：US251179
申请日：1988-09-30
申请人： Katsuya Okumura , Toshinori Shinki , Toshiaki Idaka , Riichirou Aoki
发明人： Katsuya Okumura , Toshinori Shinki , Toshiaki Idaka , Riichirou Aoki
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , Y10S257/915
摘要： A semiconductor device and a method of manufacturing the same wherein first and second wirings with an interlayer insulating film interposed therebetween are connected through a contact hole formed in the interlayer insulating film. In the semiconductor device, the first and second wirings are connected via a low resistive, conductive metal layer obtained by reducing a highly resistive oxide layer with a highly oxidizing metal, the highly resistive oxide layer being exposed within the contact hole on the surface of the first wiring. In the method of manufacturing a semiconductor device, a contact hole is opened in the interlayer insulation on the first wiring, a highly oxidizing metal is deposited on the highly resistive oxide layer on the surface of the first wiring within the contact hole, and the highly resistive oxide layer is reduced with the highly oxidizing metal to change the highly resistive oxide layer to a low resistive, conductive metal layer. The second wiring is connected to the first wiring via the conductive metal layer. The reduction may be carried out before or after depositing the second wiring, or at the time when the highly oxidizing metal is deposited.

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