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1. 发明授权

US5267198A Static memory containing sense amp and sense amp switching circuit 失效
标题翻译：包含读出放大器和感测放大器开关电路的静态存储器
公开(公告)号：US5267198A
公开(公告)日：1993-11-30
申请号：US953747
申请日：1992-09-29
申请人： Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Yasuhiko Saigou , Hiroshi Fukuta , Kunio Uchiyama , Hirokazu Aoki , Osamu Nishii
发明人： Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Yasuhiko Saigou , Hiroshi Fukuta , Kunio Uchiyama , Hirokazu Aoki , Osamu Nishii
IPC分类号： G11C11/419 , G06F12/08 , G11C7/06 , G11C11/40 , G11C11/41 , H01L27/10
CPC分类号： G11C7/065
摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.
摘要翻译：静态存储单元与字线和数据线连接。第一和第二开关串联连接在数据线和输出电路之间。读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

2. 发明授权

US5193075A Static memory containing sense AMP and sense AMP switching circuit 失效
标题翻译：静态存储器包含检测AMP和感测AMP开关电路
公开(公告)号：US5193075A
公开(公告)日：1993-03-09
申请号：US490745
申请日：1990-03-08
申请人： Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Yasuhiko Saigou , Hiroshi Fukuta , Kunio Uchiyama , Hirokazu Aoki , Osamu Nishii
发明人： Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Yasuhiko Saigou , Hiroshi Fukuta , Kunio Uchiyama , Hirokazu Aoki , Osamu Nishii
IPC分类号： G11C11/419 , G06F12/08 , G11C7/06 , G11C11/40 , G11C11/41 , H01L27/10
CPC分类号： G11C7/065
摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.
摘要翻译：静态存储单元与字线和数据线连接。第一和第二开关串联连接在数据线和输出电路之间。读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

3. 发明授权

US5202969A Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively 失效
标题翻译：单片缓存缓冲器，用于基于位和位串的指示，有选择地写入回写和独占地将数据块部分写入主存储器
公开(公告)号：US5202969A
公开(公告)日：1993-04-13
申请号：US871906
申请日：1992-04-21
申请人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
发明人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G06F12/0804 , G11C11/4096
摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
摘要翻译：在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。在缓冲寄存器和数据存储器之间连接一个选择器。该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。这种布置为高速缓冲存储器提供部分写入功能。

4. 发明授权

US5146573A Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register 失效
标题翻译：具有部分写入电路的单芯片缓存，用于在存储器和缓冲寄存器之间传输预选的数据部分
公开(公告)号：US5146573A
公开(公告)日：1992-09-08
申请号：US426781
申请日：1989-10-25
申请人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
发明人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G11C11/4096 , G06F12/0804
摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
摘要翻译：在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。在缓冲寄存器和数据存储器之间连接一个选择器。该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。这种布置为高速缓冲存储器提供部分写入功能。

5. 发明授权

US5140681A Multi-processing system and cache apparatus for use in the same 失效
标题翻译：多处理系统及其使用的缓存设备
公开(公告)号：US5140681A
公开(公告)日：1992-08-18
申请号：US355680
申请日：1989-05-23
申请人： Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Hiroshi Fukuta , Yasuhiko Saigou
发明人： Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Hiroshi Fukuta , Yasuhiko Saigou
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0815 , G06F2212/621
摘要： A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

6. 发明授权

US5287484A Multi-processor system for invalidating hierarchical cache 失效
标题翻译：用于无效分层缓存的多处理器系统
公开(公告)号：US5287484A
公开(公告)日：1994-02-15
申请号：US976645
申请日：1992-11-13
申请人： Osamu Nishii , Kunio Uchiyama , Hirokazu Aoki , Takashi Kikuchi , Yasuhiko Saigou
发明人： Osamu Nishii , Kunio Uchiyama , Hirokazu Aoki , Takashi Kikuchi , Yasuhiko Saigou
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0897
摘要： A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.
摘要翻译：关于多处理器系统中的外部和内部高速缓存的非共享系统具有多层分层高速缓存。主存储器地址总线31上的与主存储器30的重写有关的无效地址经由第一和第二路径35,36被发送到高速缓存11,21内部，以使这些内部缓存11,21无效。无效地址通过主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，以使这些外部高速缓存12,22成为无效。对于写入访问地址是非常不可能的由于外部高速缓存12,22以一个或多个拷贝的一次系统操作，所以传送到主存储器地址总线31。结果，即使无效地址经由主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，对于写入冲突的访问地址极其不可能在双向连接上有一个信号。

7. 发明授权

US5283886A Multiprocessor cache system having three states for generating invalidating signals upon write accesses 失效
标题翻译：具有三种状态的多处理器缓存系统，用于在写访问时产生无效信号
公开(公告)号：US5283886A
公开(公告)日：1994-02-01
申请号：US950746
申请日：1992-09-24
申请人： Osamu Nishii , Kunio Uchiyama , Hirokazu Aoki , Kanji Oishi , Jun Kitano , Susumu Hatano
发明人： Osamu Nishii , Kunio Uchiyama , Hirokazu Aoki , Kanji Oishi , Jun Kitano , Susumu Hatano
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0833
摘要： Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.
摘要翻译：这里公开了一种多处理器系统，其包括第一和第二处理器（1001和1002），第一和第二高速缓冲存储器（100：＃1和＃2），地址总线（123），数据总线（126），无效信号线（PURGE：131）和主存储器（1004）。第一和第二高速缓存存储器通过复制方法操作。第一高速缓存（100：＃1）的数据的状态存在于从由无效的第一状态，有效和未更新的第二状态以及有效和更新的第三状态组成的组中选择的一个状态中。第二个缓存（100：＃2）被构造成像第一个缓存。当第一处理器的写入访问第一高速缓存时，第一高速缓存的数据的状态从第二状态转移到第三状态，并且第一高速缓存将写入命中的地址和无效信号输出到地址总线和无效信号线。当来自第一处理器的写访问错过第一高速缓存时，一个块的数据被从主存储器块传输到第一高速缓存，并且输出无效信号。之后，第一个缓存执行传输块中数据的写入。在第一和第二高速缓冲存储器将存取请求地址与相关地址相关的第三状态的数据保存到地址总线（123）的情况下，相关高速缓冲存储器将相关数据写回到主存储器中。

8. 发明授权

US06879188B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06879188B2
公开(公告)日：2005-04-12
申请号：US10322594
申请日：2002-12-19
申请人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
发明人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
IPC分类号： G06F1/04 , G06F1/06 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03L7/07 , H03L7/081 , H03L7/099 , H03B19/00
CPC分类号： H03L7/07 , G06F1/04 , G06F1/3203 , H03L7/0812 , H03L7/0995 , Y02D10/126
摘要： A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.
摘要翻译：一种采用两个时钟信号发生电路的半导体集成电路器件，其输出时钟信号以分配到器件的内部电路，具有不同时钟稳定时间的第一和第二时钟信号发生电路及其选择是从器件外部实现的。时钟信号发生电路中的第一个使用例如具有大的时钟稳定时间的锁相环电路，并且第二时钟信号发生电路例如使用延迟锁定环电路来实现，时钟建立时间很小，例如2-3个周期。由于具有小的时钟建立时间的第二时钟信号产生电路的选择性致动，当器件的内部电路停止时也可以停止内部电路的时钟信号的产生，从而进一步降低功耗而不会影响时钟振荡器的响应。

9. 发明授权

US06515519B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06515519B1
公开(公告)日：2003-02-04
申请号：US09580646
申请日：2000-05-30
申请人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
发明人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
IPC分类号： H03B1900
CPC分类号： H03L7/07 , G06F1/04 , G06F1/3203 , H03L7/0812 , H03L7/0995 , Y02D10/126
摘要： A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.
摘要翻译：来自晶体谐振器或外部时钟信号的信号从端子xta1或exta1输入，并且来自晶体谐振器或外部时钟信号的信号由模式端子mod8选择并输入到振荡器OSC。输入时钟信号ck11由分频器DIV1分频为期望值。输入分频时钟信号clk2作为锁相环路PLL1或延迟锁定环路DLL1的基准时钟，由选择器SEL3选择的电路输出的时钟信号通过分配器DIV2通过分配给LSI。锁相环PLL1具有至少40个时钟周期的时钟建立时间，而延迟锁定环DLL1的时钟建立时间为2-3个周期。

10. 发明授权

US5386394A Semiconductor memory device for performing parallel operations on hierarchical data lines 失效
标题翻译：用于在分层数据线上执行并行操作的半导体存储器件
公开(公告)号：US5386394A
公开(公告)日：1995-01-31
申请号：US114633
申请日：1993-09-02
申请人： Takayuki Kawahara , Masakazu Aoki , Yoshinobu Nakagome , Makoto Hanawa , Kunio Uchiyama , Masayuki Nakamura , Goro Kitsukawa , Kanji Oishi
发明人： Takayuki Kawahara , Masakazu Aoki , Yoshinobu Nakagome , Makoto Hanawa , Kunio Uchiyama , Masayuki Nakamura , Goro Kitsukawa , Kanji Oishi
IPC分类号： G06F12/08 , G11C7/10 , G11C11/401 , G11C11/409 , G11C7/00 , G11C11/40
CPC分类号： G11C7/1048 , G11C7/1006
摘要： The semiconductor device has more-significant global data lines and less-significant data lines hierarchically formed, and switches for controlling the more-significant global data lines and the less-significant data lines to be connected each other. In addition, the semiconductor device has the unit for precharging the global data lines independently of the data lines.
摘要翻译：半导体器件具有分层形成的更重要的全局数据线和较不重要的数据线，以及用于控制更有意义的全局数据线和不太重要的数据线彼此连接的开关。此外，半导体器件具有用于独立于数据线预充电全局数据线的单元。

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