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1. 发明授权

US06879188B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06879188B2
公开(公告)日：2005-04-12
申请号：US10322594
申请日：2002-12-19
申请人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
发明人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
IPC分类号： G06F1/04 , G06F1/06 , G06F1/32 , H01L21/82 , H01L21/822 , H01L27/04 , H03L7/07 , H03L7/081 , H03L7/099 , H03B19/00
CPC分类号： H03L7/07 , G06F1/04 , G06F1/3203 , H03L7/0812 , H03L7/0995 , Y02D10/126
摘要： A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.
摘要翻译：一种采用两个时钟信号发生电路的半导体集成电路器件，其输出时钟信号以分配到器件的内部电路，具有不同时钟稳定时间的第一和第二时钟信号发生电路及其选择是从器件外部实现的。时钟信号发生电路中的第一个使用例如具有大的时钟稳定时间的锁相环电路，并且第二时钟信号发生电路例如使用延迟锁定环电路来实现，时钟建立时间很小，例如2-3个周期。由于具有小的时钟建立时间的第二时钟信号产生电路的选择性致动，当器件的内部电路停止时也可以停止内部电路的时钟信号的产生，从而进一步降低功耗而不会影响时钟振荡器的响应。

2. 发明申请

US20050050309A1 Data processor 审中-公开
标题翻译：数据处理器
公开(公告)号：US20050050309A1
公开(公告)日：2005-03-03
申请号：US10927199
申请日：2004-08-27
申请人： Hajime Yamashita , Kiwamu Takada , Takahiro Irita , Toru Hiraoka
发明人： Hajime Yamashita , Kiwamu Takada , Takahiro Irita , Toru Hiraoka
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/3844 , G06F9/3861
摘要： A data processor for executing branch prediction comprises a queuing buffer (23) allocated to an instruction queue and to a return destination instruction queue and having address pointers managed for each instruction stream and a control portion (21) for the queuing buffer. The control portion stores a prediction direction instruction stream and a non-prediction direction instruction stream in the queuing buffer and switches an instruction stream as an execution object from the prediction direction instruction stream to the non-prediction direction instruction stream inside the queuing buffer in response to failure of branch prediction. When buffer areas (Qa1, Qb) are used as the instruction queue, the buffer area (Qa2) is used as a return instruction queue and the buffer area (Qa1) is used as a return instruction queue. A return operation of a non-prediction direction instruction string at the time of failure of branch prediction is accomplished by stream management without using fixedly and discretely the instruction queue and the return destination instruction queue.
摘要翻译：用于执行分支预测的数据处理器包括分配给指令队列和返回目的地指令队列的排队缓冲器（23），并且具有为每个指令流管理的地址指针和用于排队缓冲器的控制部分（21）。控制部分将预测方向指令流和非预测方向指令流存储在排队缓冲器中，并将作为执行对象的指令流从预测方向指令流切换到排队缓冲器内的非预测方向指令流，作为响应分支预测失败。当使用缓冲区（Qa1，Qb）作为指令队列时，缓冲区（Qa2）用作返回指令队列，缓冲区（Qa1）用作返回指令队列。在分支预测失败时的非预测方向指令串的返回操作是通过流管理完成的，而不用固定地和离散地使用指令队列和返回目的地指令队列。

3. 发明授权

US06515519B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06515519B1
公开(公告)日：2003-02-04
申请号：US09580646
申请日：2000-05-30
申请人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
发明人： Masayuki Miyazaki , Ken Tatezawa , Kiwamu Takada , Kunio Uchiyama , Osamu Nishii , Kiyoshi Hasegawa , Hirokazu Aoki , Masaru Kokubo
IPC分类号： H03B1900
CPC分类号： H03L7/07 , G06F1/04 , G06F1/3203 , H03L7/0812 , H03L7/0995 , Y02D10/126
摘要： A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.
摘要翻译：来自晶体谐振器或外部时钟信号的信号从端子xta1或exta1输入，并且来自晶体谐振器或外部时钟信号的信号由模式端子mod8选择并输入到振荡器OSC。输入时钟信号ck11由分频器DIV1分频为期望值。输入分频时钟信号clk2作为锁相环路PLL1或延迟锁定环路DLL1的基准时钟，由选择器SEL3选择的电路输出的时钟信号通过分配器DIV2通过分配给LSI。锁相环PLL1具有至少40个时钟周期的时钟建立时间，而延迟锁定环DLL1的时钟建立时间为2-3个周期。

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