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1. 发明授权

US06314511B1 Mechanism for freeing registers on processors that perform dynamic out-of-order execution of instructions using renaming registers 失效
公开(公告)号：US06314511B1
公开(公告)日：2001-11-06
申请号：US09054100
申请日：1998-04-02
申请人： Henry M. Levy , Susan J. Eggers , Jack Lo , Dean M. Tullsen
发明人： Henry M. Levy , Susan J. Eggers , Jack Lo , Dean M. Tullsen
IPC分类号： G06F938
摘要： A system and a method is described for freeing renaming registers that have been allocated to architectural registers prior to another instruction redefining the architectural register. Renaming registers are used by a processor to dynamically execute instructions out-of-order. The present invention may be employed by any single or multi-threaded processor that executes instructions out-of-order. A mechanism is described for freeing renaming registers that consists of a set of instructions, used by a compiler, to indicate to the processor when it can free the physical (renaming) register that is allocated to a particular architectural register. This mechanism permits the renaming register to be reassigned or reallocated to store another value as soon as the renaming register is no longer needed for allocation to the architectural register. There are at least three ways to enable the processor with an instruction that identifies the renaming register to be freed from allocation: (1) a user may explicitly provide the instruction to the processor that refers to a particular renaming register; (2) an operating system may provide the instruction when a thread is idle that refers to a set of registers associated with the thread; and (3) a compiler may include the instruction with the plurality of instructions presented to the processor. There are at least five embodiments of the instruction provided to the processor for freeing renaming registers allocated to architectural registers: (1) Free Register Bit; (2) Free Register; (3) Free Mask; (4) Free Opcode; and (5) Free Opcode/Mask. The Free Register Bit instruction provides the largest speedup for an out-of-order processor and the Free Register instruction provides the smallest speedup.

2. 发明授权

US6092175A Shared register storage mechanisms for multithreaded computer systems with out-of-order execution 失效
标题翻译：具有无序执行的多线程计算机系统的共享寄存器存储机制
公开(公告)号：US6092175A
公开(公告)日：2000-07-18
申请号：US53903
申请日：1998-04-02
申请人： Henry M. Levy , Susan J. Eggers , Jack Lo , Dean M. Tullsen
发明人： Henry M. Levy , Susan J. Eggers , Jack Lo , Dean M. Tullsen
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/46
CPC分类号： G06F9/30123 , G06F9/30076 , G06F9/3836 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/462
摘要： A method and organization for implementing the registers required in a computer system supporting multithreading and dynamic out-of-order execution. Multithreaded computer systems are those in which the processor supports multiple contexts (threads), and either rapid context switching from thread to thread or scheduling of instructions from different threads within a single cycle. An important component of processors for such systems is the register file; the processor needs a large register file or resource to provide the registers used for the threads. One form of the invention maintains a set of private architecturally specified registers, and a set of private renaming register for each different thread. In the other three embodiments, sharing of renaming registers between different threads is permitted, to enable a reduction in the total number of registers required. One of these three embodiments enables any of the architecturally specified registers that are private to a thread but are not in use, to be employed as renaming registers. Another of the embodiments treats all registers as sharable and enables any register from the register file or resource to be used as a renaming register for any thread.
摘要翻译：一种用于实现支持多线程和动态无序执行的计算机系统中所需的寄存器的方法和组织。多线程计算机系统是处理器支持多个上下文（线程），以及从单线程到线程的快速上下文切换或来自单个周期内不同线程的指令调度的系统。这种系统的处理器的一个重要组成部分是寄存器文件; 处理器需要一个大的寄存器文件或资源来提供用于线程的寄存器。本发明的一种形式维护一组私有结构上指定的寄存器，以及一组用于每个不同线程的私有重命名寄存器。在其他三个实施例中，允许在不同线程之间共享重命名寄存器，以便能够减少所需的寄存器总数。这三个实施例中的一个使得任何对线程是私有的但不被使用的架构地指定的寄存器被用作重命名寄存器。另一个实施例将所有寄存器视为可共享的，并且使来自寄存器文件或资源的任何寄存器能够用作任何线程的重命名寄存器。

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