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    • 2. 发明授权
    • Power amplifier linearization
    • 功率放大器线性化
    • US07313199B2
    • 2007-12-25
    • US10357130
    • 2003-02-03
    • Deepnarayan GuptaOleg A. Mukhanov
    • Deepnarayan GuptaOleg A. Mukhanov
    • H04L25/49H04B15/00
    • H03F1/3294H03F1/3247H03F2200/294H03F2200/331H03F2200/372H04L27/367H04L27/368
    • A system for linearizing the output of a high power amplifier (HPA) designed to transmit an RF modulated signal includes in its transmit section a digital up-converter for processing baseband input signals and generating a desired digital RF waveform, T(s). The desired digital RF waveform T(s) is then fed to a digital predistorter circuit for producing a predistorted digital RF waveform P(s)T(s) which, as modified, may be applied via a high sampling speed high linearity digital to analog converter to the high power amplifier (HPA) to produce an output signal which is a linear function of the baseband input signal. The digital predistorter circuit may be of the adaptive type or of the predictive type. Circuits embodying the invention may include encoding circuitry for converting multi-bit signals to a serial stream of single-bit pulses for enabling simplification in the digital to analog conversion. In accordance with the invention, corrections for non-linearity of the HPA may be made directly on the RF waveform using ultra-high speed superconducting electronics (SCE) and decreasing the time delay between sensing a transmitted signal and generating a correcting (linearizing) signal.
    • 用于线性化用于发送RF调制信号的高功率放大器(HPA)的输出的系统在其发射部分中包括用于处理基带输入信号并产生期望的数字RF波形T(s)的数字上变频器。 然后将期望的数字RF波形T(s)馈送到数字预失真器电路,用于产生预失真的数字RF波形P(s)T(s),其经修改,可以经由高采样速度高线性度数字到模拟 转换器到高功率放大器(HPA)以产生作为基带输入信号的线性函数的输出信号。 数字预失真器电路可以是自适应型或预测型。 体现本发明的电路可以包括用于将多位信号转换为单位脉冲串行流的编码电路,以实现数模转换的简化。 根据本发明,可以使用超高速超导电子器件(SCE)在RF波形上直接进行HPA的非线性校正,并且减小感测发射信号和产生校正(线性化)信号之间的时间延迟 。
    • 6. 发明授权
    • Digital receiver for radio-frequency signals
    • 数字接收机用于射频信号
    • US07991013B2
    • 2011-08-02
    • US11966889
    • 2007-12-28
    • Deepnarayan GuptaOleg A. Mukhanov
    • Deepnarayan GuptaOleg A. Mukhanov
    • H04L27/06H04B1/06G06F1/04H03K19/00H03K19/195
    • H03K17/92H04B1/005H04B1/0483H04B1/40H04B1/44
    • A system and method for receiving radio frequency signals, comprising a plurality of analog signal couplers, for communicating a representation of a radio frequency signal; a respective analog to digital converter for each of said couplers, each having an output presenting a digital representation of the representation and an associated clock; a non-blocking switch matrix, receiving the plurality of outputs and associated clocks, and producing a plurality of regenerated outputs and associated regenerated clocks under selective control of a switch matrix signal; and a plurality of digital radio frequency signal processors, adapted to receive at least one regenerated output from the non-blocking switch matrix and associated regenerated clock.
    • 一种用于接收射频信号的系统和方法,包括多个模拟信号耦合器,用于传送射频信号的表示; 用于每个所述耦合器的相应模拟到数字转换器,每个具有呈现所述表示的数字表示的输出和相关联的时钟; 非阻塞开关矩阵,接收多个输出和相关联的时钟,并且在开关矩阵信号的选择性控制下产生多个再生输出和相关联的再生时钟; 以及多个数字射频信号处理器,适于从非阻塞开关矩阵和相关联的再生时钟接收至少一个再生输出。
    • 7. 发明申请
    • Ultra fast circuitry for digital filtering
    • 用于数字滤波的超快速电路
    • US20080231353A1
    • 2008-09-25
    • US11895478
    • 2007-08-24
    • Timur V. FilippovOleg A. Mukhanov
    • Timur V. FilippovOleg A. Mukhanov
    • H04B1/10
    • H01L39/045H01L39/025H01L39/2493H03K5/13H03K2005/00286H05K13/0469
    • The invention includes a novel differentiator cell, a novel resample unit cell, and precision synchronization circuitry to ensure proper timing of the circuits and systems at the anticipated ultra-high speed of operation. The novel differentiator cell includes circuitry for combining a carry input signal, a data bit signal and the output signal of a NOT cell and applying the signals as distinct and separate pulses to the input of a toggle flip-flop (TFF) for producing an asynchronous carry output and a clocked data output. The novel differentiator cells can be interconnected to form a multi-bit differentiator circuit using appropriate delay and synchronization circuitry to compensate for delays in producing the carry output of each cell which is applied to a succeeding cell. The novel resample cell includes a non-destructive reset-set flip-flop (RSN) designed to receive a data bit, at its set input, at a slow clock rate, which data is repeatedly read out of the RSN at a fast clock rate, until the RSN is reset. The novel differentiator and resampler cells can be interconnected, for example, to form the differentiator and up-sampling sections of a digital interpolation filter (DIF). Also, the relative clocking of bit slices (columns) in such a DIF may be achieved by using the fast clock signal to synchronize the slow clock which controls data entry. The circuits of the invention can be advantageously implemented with Josephson Junctions in rapid-single-flux-quantum (RSFQ) logic.
    • 本发明包括一种新颖的微分单元,一种新的重采样单元,以及精确同步电路,用于确保在预期的超高速操作下电路和系统的正确定时。 新颖的微分器单元包括用于组合进位输入信号,数据位信号和NOT单元的输出信号的电路,并且将该信号作为截止触发器(TFF)的输入施加到截止触发器(TFF)的输入端,以产生异步 携带输出和时钟数据输出。 新颖的微分器单元可以互连以形成使用适当的延迟和同步电路的多位微分电路,以补偿产生应用于后续单元的每个单元的进位输出的延迟。 新型重采样单元包括一个非破坏性的复位触发器(RSN),它被设计为在其设定的输入处以慢的时钟速率接收一个数据位,该数据以快速时钟速率从RSN重复读出 ,直到RSN复位。 新颖的微分器和重采样器单元可以互连,例如形成数字插值滤波器(DIF)的微分器和上采样部分。 此外,这种DIF中的位片(列)的相对时钟可以通过使用快速时钟信号来同步控制数据输入的慢时钟来实现。 本发明的电路可以有利地用快速单通量 - 量子(RSFQ)逻辑中的约瑟夫逊接合来实现。