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    • 8. 发明授权
    • Double gate MOS transistors
    • 双栅MOS晶体管
    • US06940129B2
    • 2005-09-06
    • US10715664
    • 2003-11-18
    • Sung-Min KimDong-Gun ParkChang-Sub LeeJeong-Dong ChoeShin-Ae LeeSeong-Ho Kim
    • Sung-Min KimDong-Gun ParkChang-Sub LeeJeong-Dong ChoeShin-Ae LeeSeong-Ho Kim
    • H01L29/78H01L21/336H01L21/84H01L27/12H01L29/786
    • H01L29/66772H01L21/84H01L27/1203H01L29/78621H01L29/78645H01L29/78648H01L29/78654
    • A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode. The top gate electrode overlaps with the bottom gate electrode and is insulated from the transistor active region. Methods of fabricating such transistors are also provided.
    • 双栅MOS晶体管包括限定在半导体衬底中的衬底有源区和位于衬底有源区上方并与衬底有源区重叠的晶体管有源区。 至少一个半导体柱穿透晶体管有源区并与衬底有源区接触。 半导体柱支撑晶体管有源区,使得晶体管有源区与衬底有源区间隔开。 至少一个底栅电极填充晶体管有源区和衬底有源区之间的空间。 底栅电极与衬底有源区,晶体管有源区和半导体柱绝缘。 至少一个顶栅电极跨越晶体管有源区,并且具有与底栅电极的侧壁接触的至少一个端。 顶栅电极与底栅电极重叠并与晶体管有源区绝缘。 还提供制造这种晶体管的方法。