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1. 发明申请

US20080272422A1 Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof 有权
标题翻译：提供不同阈值电压的晶体管及其制造方法
公开(公告)号：US20080272422A1
公开(公告)日：2008-11-06
申请号：US11743973
申请日：2007-05-03
申请人： Sung-Ki Min
发明人： Sung-Ki Min
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/66659
摘要： A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.
摘要翻译：晶体管包括具有第一部分和第二部分的沟道区域。第一部分的长度小于第二部分的长度。第一部分具有比第二部分更高的阈值电压。第二部分的较低阈值电压允许增加的导通电流。尽管在导通电流中获得了增加，第一部分的较高阈值电压维持或降低了晶体管的相对较低的截止电流。

2. 发明授权

US5173760A BiCMOS semiconductor device 失效
标题翻译： BiCMOS半导体器件
公开(公告)号：US5173760A
公开(公告)日：1992-12-22
申请号：US498590
申请日：1990-03-26
申请人： Sung-Ki Min , Chang-Won Kahng , Uk-Rae Cho , Jong-Mil Youn , Suk-Gi Choi
发明人： Sung-Ki Min , Chang-Won Kahng , Uk-Rae Cho , Jong-Mil Youn , Suk-Gi Choi
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249
摘要： A method for fabricating a BiCMOS device to achieve a maximum performance through a minimum processing steps, in which the BiCMOS device comprises high integration and high performance MOS transistors, self-aligned metal contact emitter type bipolar transistors having high load driving force, high performance matching characteristics and high integration, and self-aligned polycrystalline silicon emitter type bipolar transistors having high integration and high speed characteristics in low current, thereby being used in high integration, high speed digital and precise analog system. Said method comprises a plurality of fabrication steps including ion-implantation, formation of thin film oxide layer, deposition of nitride layer, etching of oxide layer, formation of windows and others, alternately or/and sequentially in a single chip substrate.
摘要翻译：一种用于制造BiCMOS器件以通过最小处理步骤实现最大性能的方法，其中BiCMOS器件包括高集成度和高性能MOS晶体管，具有高负载驱动力的自对准金属接触发射极型双极晶体管，高性能匹配特性和高集成度，以及在低电流下具有高集成度和高速特性的自对准多晶硅发射极型双极晶体管，从而被用于高集成度，高速数字和精确模拟系统。所述方法包括在单个芯片衬底中交替地或/或顺序地包括离子注入，薄膜氧化物层的形成，氮化物层的沉积，氧化物层的蚀刻，窗口的形成等多个制造步骤。

3. 发明授权

US4970174A Method for making a BiCMOS semiconductor device 失效
标题翻译：制造BiCMOS半导体器件的方法
公开(公告)号：US4970174A
公开(公告)日：1990-11-13
申请号：US244810
申请日：1988-09-15
申请人： Sung-Ki Min , Chang-Won Kahng , Uk-Rae Cho , Jong-Mil Youn , Sukgi Choi
发明人： Sung-Ki Min , Chang-Won Kahng , Uk-Rae Cho , Jong-Mil Youn , Sukgi Choi
IPC分类号： H01L29/73 , H01L21/302 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L29/732
CPC分类号： H01L21/8249 , Y10S148/009 , Y10S148/124
摘要： A method with less processing steps for making a BiCMOS semiconductor device which can be used both in high-integration, high-speed digital devices and in precise analog devices by forming within a single substrate a CMOS transistor, a metal contact emitter bipolymer transistor having the high load driving power and highly effective matching characteristics, and a polycrystalline silicon emitter bipolar transistor having a high-speed characteristic at a low current level. Said device includes a first and a second MOSFET, and a first and a second bipolar transistor on a first conductivity-type silicon substrate, wherein performing a second conductivity-type of ion-implantation for producing a first substrate region to thereon form the first MOSFET, and a third and a fourth substrate region to thereon form the first and second bipolar transistors, respectively on said substrate. The second MOSFET is subsequently formed in a second substrate region being located between the first and third substrate regions.
摘要翻译：一种具有较少处理步骤的方法，用于制造BiCMOS半导体器件，其可以在高集成度，高速数字器件和精确模拟器件中使用，通过在单个衬底内形成CMOS晶体管，金属接触发射二极管晶体管具有高负载驱动功率和高效匹配特性，以及在低电流水平下具有高速特性的多晶硅发射极双极晶体管。所述器件包括第一和第二MOSFET，以及在第一导电型硅衬底上的第一和第二双极晶体管，其中执行用于产生第一衬底区域的第二导电类型的离子注入形成第一MOSFET 以及分别在所述衬底上形成第一和第二双极晶体管的第三和第四衬底区域。随后在位于第一和第三衬底区域之间的第二衬底区域中形成第二MOSFET。

4. 发明授权

US07843018B2 Transistor providing different threshold voltages and method of fabrication thereof 失效
公开(公告)号：US07843018B2
公开(公告)日：2010-11-30
申请号：US12363796
申请日：2009-02-02
申请人： Sung-Ki Min
发明人： Sung-Ki Min
IPC分类号： H01L29/00
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/66659
摘要： A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.

5. 发明申请

US20090134475A1 Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof 失效
标题翻译：提供不同阈值电压的晶体管及其制造方法
公开(公告)号：US20090134475A1
公开(公告)日：2009-05-28
申请号：US12363796
申请日：2009-02-02
申请人： Sung-Ki Min
发明人： Sung-Ki Min
IPC分类号： H01L29/78
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/66659
摘要： A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.
摘要翻译：晶体管包括具有第一部分和第二部分的沟道区域。第一部分的长度小于第二部分的长度。第一部分具有比第二部分更高的阈值电压。第二部分的较低阈值电压允许增加的导通电流。尽管在导通电流中获得了增加，第一部分的较高阈值电压维持或降低了晶体管的相对较低的截止电流。

6. 发明申请

US20090024377A1 System and Method for Modeling Semiconductor Devices Using Pre-Processing 审中-公开
标题翻译：使用预处理建模半导体器件的系统和方法
公开(公告)号：US20090024377A1
公开(公告)日：2009-01-22
申请号：US11778454
申请日：2007-07-16
申请人： Sung-Ki Min
发明人： Sung-Ki Min
IPC分类号： G06G7/62
CPC分类号： G06F17/5036
摘要： A system for modeling a semiconductor device comprises a pre-processing module and a simulation module. The pre-processing module stores at least one virtual model equation associated with at least one terminal of a semiconductor device. The pre-processing module receives an actual voltage value associated with the at least one terminal. The pre-processing module then calculates at least one modified voltage value for the at least one terminal based at least in part upon the virtual model equation and the actual voltage value. The simulation module receives the modified voltage value, and generates a simulation result for the semiconductor device based at least in part upon the modified voltage value.
摘要翻译：用于对半导体器件建模的系统包括预处理模块和仿真模块。预处理模块存储与半导体器件的至少一个端子相关联的至少一个虚拟模型方程。预处理模块接收与至少一个终端相关联的实际电压值。预处理模块至少部分地基于虚拟模型方程和实际电压值来计算至少一个终端的至少一个修改的电压值。模拟模块接收修改的电压值，并且至少部分地基于修改的电压值来生成半导体器件的模拟结果。

7. 发明授权

US4826783A Method for fabricating a BiCMOS device 失效
标题翻译： BiCMOS器件制造方法
公开(公告)号：US4826783A
公开(公告)日：1989-05-02
申请号：US106582
申请日：1987-10-08
申请人： Suki-Gi Choi , Sung-Ki Min , Chang-Won Kahng
发明人： Suki-Gi Choi , Sung-Ki Min , Chang-Won Kahng
IPC分类号： H01L29/94 , H01L21/331 , H01L21/78 , H01L21/8249 , H01L27/06 , H01L29/73 , H01L21/70
CPC分类号： H01L21/8249 , Y10S148/009
摘要： This invention provides a method for fabricating a BiCMOS device, in which said device has a Si substrate of a first conductivity in which there is formed a first substrate region of a second conductivity for a bipolar transistor, a second substrate region of said second conductivity for a first MOSFET, having a source and drain of the first conductivity, and in which a part of said Si substrate is formed to provide a second MOSFET which has a source and drain of the second conductivity. A first nitride layer is used to prevent the substrate under a masking layer from oxidizing during the following oxidation processes, wherein the masking layer is composed of a oxide layer and the nitride layer. After some processes, the masking layer is removed. Implanting As impurities, a new oxide layer and a new nitride layer are deposited, wherein the role of the nitride layer is to protect a shallow emitter region. After that, a new clean oxide layer is grown for a gate insulator layer, and controllable clean gate oxide layer is obtained.
摘要翻译：本发明提供一种制造BiCMOS器件的方法，其中所述器件具有第一导电性的Si衬底，其中形成用于双极晶体管的第二导电性的第一衬底区域，所述第二导电性的第二衬底区域用于第一MOSFET，其具有第一导电性的源极和漏极，并且其中形成所述Si衬底的一部分以提供具有第二导电性的源极和漏极的第二MOSFET。第一氮化物层用于防止掩模层下的衬底在随后的氧化过程中氧化，其中掩模层由氧化物层和氮化物层组成。在一些处理之后，去除掩模层。植入作为杂质，沉积新的氧化物层和新的氮化物层，其中氮化物层的作用是保护浅的发射极区域。之后，为栅极绝缘体层生长新的清洁氧化物层，并获得可控的清洁栅极氧化物层。

8. 发明授权

US07645662B2 Transistor providing different threshold voltages and method of fabrication thereof 有权
标题翻译：提供不同阈值电压的晶体管及其制造方法
公开(公告)号：US07645662B2
公开(公告)日：2010-01-12
申请号：US11743973
申请日：2007-05-03
申请人： Sung-Ki Min
发明人： Sung-Ki Min
IPC分类号： H01L21/8238
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/66659
摘要： A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.
摘要翻译：晶体管包括具有第一部分和第二部分的沟道区域。第一部分的长度小于第二部分的长度。第一部分具有比第二部分更高的阈值电压。第二部分的较低阈值电压允许增加的导通电流。尽管在导通电流中获得了增加，第一部分的较高阈值电压维持或降低了晶体管的相对较低的截止电流。

9. 发明授权

US07388440B1 Circuit and method to speed up PLL lock-time and prohibit frequency runaway 有权
标题翻译：加速PLL锁定时间的电路和方法，禁止频率失控
公开(公告)号：US07388440B1
公开(公告)日：2008-06-17
申请号：US11003996
申请日：2004-12-02
申请人： Gary Giust , Chwei-Po Chew , Sung-Ki Min
发明人： Gary Giust , Chwei-Po Chew , Sung-Ki Min
IPC分类号： H03L
CPC分类号： H03L7/10
摘要： A lock-aid circuit and method is applied to a phase lock loop (PLL) having a voltage controlled oscillator (VCO), wherein the lock aid is coupled with the input of the VCO. In one example, the lock aid includes a Schmitt trigger having an output, a switch having an output and an input coupled to the output of the Schmitt trigger, and a voltage controlled current source coupled with the output of the switch.
摘要翻译：锁相电路和方法应用于具有压控振荡器（VCO）的锁相环（PLL），其中锁定辅助装置与VCO的输入耦合。在一个示例中，锁定辅助装置包括具有输出的施密特触发器，具有输出的开关和耦合到施密特触发器的输出的输入以及与开关的输出端耦合的压控电流源。

10. 发明授权

US4912055A Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4912055A
公开(公告)日：1990-03-27
申请号：US265420
申请日：1988-10-31
申请人： Sung-Ki Min , Chang-Won Kahng , Uk-Rae Cho , Jong-Mil Youn , Suk-Gi Choi
发明人： Sung-Ki Min , Chang-Won Kahng , Uk-Rae Cho , Jong-Mil Youn , Suk-Gi Choi
IPC分类号： H01L29/73 , C08G18/30 , C08G18/32 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/10 , H01L29/732
CPC分类号： H01L21/8249
摘要： A method for fabricating a BiCMOS device to achieve a maximum performance through a of minimum processing steps, in which the BiCMOS device is exemplary for its high integration and high performance MOS transistors, self-aligned metal contact emitter type bipolar transistors having high load driving force, high performance matching characteristics and high integration, and self-aligned polycrystalline silicon emitter type bipolar transistors having high integration and high speed characteristics in low current, thereby being used in high integration, high speed digital and precise analog system. The method includes a plurality of fabrication steps including ion-implantation, formation of a thin film oxide layer, deposition of a nitride layer, etching of the oxide layer, formation of windows and others, alternately and/or sequentially in a single chip substrate.
摘要翻译：一种用于制造BiCMOS器件以通过最小处理步骤实现最大性能的方法，其中BiCMOS器件是其高集成度和高性能MOS晶体管的示例性，具有高负载驱动力的自对准金属接触发射极型双极晶体管，高性能匹配特性和高集成度，以及在低电流下具有高集成度和高速特性的自对准多晶硅发射极型双极晶体管，从而被用于高集成度，高速数字和精确模拟系统。该方法包括在单个芯片衬底中交替地和/或顺序地包括离子注入，薄膜氧化物层的形成，氮化物层的沉积，氧化物层的蚀刻，窗口等的形成的多个制造步骤。

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