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1. 发明授权

US06984594B2 Deposition method of insulating layers having low dielectric constant of semiconductor devices 有权
标题翻译：具有低介电常数半导体器件的绝缘层的沉积方法
公开(公告)号：US06984594B2
公开(公告)日：2006-01-10
申请号：US10150480
申请日：2002-05-17
申请人： Sung-Hoon Yang , Glenn A. Cerny , Kyuha Chung , Byung-Keun Hwang , Wan-Shick Hong
发明人： Sung-Hoon Yang , Glenn A. Cerny , Kyuha Chung , Byung-Keun Hwang , Wan-Shick Hong
IPC分类号： H01L21/31
CPC分类号： H01L21/02126 , C23C16/401 , G02F1/1362 , H01L21/02211 , H01L21/02274 , H01L21/31633 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a process for vapor depositing alow dielectric insulating film, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device.
摘要翻译：本发明涉及一种用于气相沉积低介电绝缘膜的方法，更具体地说涉及一种低介电绝缘膜的气相淀积工艺，可以显着提高蒸镀速度，同时保持低介电绝缘膜的性能，从而解决寄生实现高开口率结构的电容问题，并且可以通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时减少处理时间，从而形成用于半导体器件的保护膜。

2. 发明授权

US07075601B2 Thin film transistor array for a liquid crystal display having a data line cross-connection 有权
标题翻译：用于具有数据线交叉连接的液晶显示器的薄膜晶体管阵列
公开(公告)号：US07075601B2
公开(公告)日：2006-07-11
申请号：US10470116
申请日：2002-02-26
申请人： Mun-Pyo Hong , Wan-Shick Hong , Nam-Seok Roh , Kyuha Chung , Chong-Chul Chai
发明人： Mun-Pyo Hong , Wan-Shick Hong , Nam-Seok Roh , Kyuha Chung , Chong-Chul Chai
IPC分类号： G02F1/1335
CPC分类号： G02F1/133514 , G02F2201/52
摘要： Pixels of red, blue and green are sequentially arranged in the row direction. The red and green pixels are alternately arranged in the column while the blue pixels being arranged between the neighboring red and each blue pixel is surrounded by the four red and green pixels. Gate lines are arranged at respective pixel rows. Data lines cross over the gate lines in an insulating manner and are arranged at the respective pixel columns. Pixel electrodes and thin film transistor are arranged at the respective pixels. At a predetermined pixel unit, the data lines to the two blue pixel are connected to each other. The pixel electrodes are overlapped with the gate lines or data lines via a passivation layer of low dielectric organic material or insulating material such as SiOC, SiOF.
摘要翻译：红色，蓝色和绿色的像素依次排列在行方向。红色和绿色像素交替排列在列中，而布置在相邻红色和每个蓝色像素之间的蓝色像素被四个红色和绿色像素包围。栅极线被布置在各个像素行。数据线以绝缘方式跨越栅极线并且布置在各个像素列处。像素电极和薄膜晶体管布置在各个像素处。在预定像素单元处，到两个蓝色像素的数据线彼此连接。像素电极经由低介电有机材料的钝化层或绝缘材料如SiOC，SiOF与栅极线或数据线重叠。

3. 发明授权

US07323371B2 Deposition method of insulating layers having low dielectric constant of semiconductor device, a thin film transistor substrate using the same and a method of manufacturing the same 有权
标题翻译：具有低介电常数的半导体器件的绝缘层的沉积方法，使用其的薄膜晶体管基板及其制造方法
公开(公告)号：US07323371B2
公开(公告)日：2008-01-29
申请号：US11071544
申请日：2005-03-03
申请人： Sung-Hoon Yang , Wan-Shick Hong , Kwan-Wook Jung
发明人： Sung-Hoon Yang , Wan-Shick Hong , Kwan-Wook Jung
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： G02F1/136227 , C23C16/30 , G02F2001/136222 , H01L27/12 , H01L27/1248 , H01L27/1288 , H01L27/3244 , H01L29/458 , H01L29/4908 , H01L51/56
摘要： The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.
摘要翻译：本发明涉及一种用于气相沉积低介电绝缘膜的方法，使用其的薄膜晶体管及其制备方法，更具体地涉及可以显着改善蒸气的低介电绝缘膜的气相沉积方法同时保持低介电绝缘膜的性能，从而解决了寄生电容问题，以实现高开口率结构，并且通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时可以减少处理时间，以形成用于半导体器件的保护膜。本发明还涉及使用该方法及其制备方法的薄膜晶体管。

4. 发明申请

US20080121890A1 DEPOSITION METHOD OF INSULATING LAYERS HAVING LOW DIELECTRIC CONSTANT OF SEMICONDUCTOR DEVICE, A THIN FILM TRANSISTOR SUBSTRATE USING THE SAME AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有半导体器件的低介电常数的绝缘层的沉积方法，使用该半导体器件的薄膜晶体管衬底及其制造方法
公开(公告)号：US20080121890A1
公开(公告)日：2008-05-29
申请号：US11950476
申请日：2007-12-05
申请人： Sung-Hoon YANG , Wan-Shick Hong , Kwan-Wook Jung
发明人： Sung-Hoon YANG , Wan-Shick Hong , Kwan-Wook Jung
IPC分类号： H01L29/786
CPC分类号： G02F1/136227 , C23C16/30 , G02F2001/136222 , H01L27/12 , H01L27/1248 , H01L27/1288 , H01L27/3244 , H01L29/458 , H01L29/4908 , H01L51/56
摘要： The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.
摘要翻译：本发明涉及一种用于气相沉积低介电绝缘膜的方法，使用其的薄膜晶体管及其制备方法，更具体地涉及可以显着改善蒸气的低介电绝缘膜的气相沉积方法同时保持低介电绝缘膜的性能，从而解决了寄生电容问题，以实现高开口率结构，并且通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时可以减少处理时间，以形成用于半导体器件的保护膜。本发明还涉及使用该方法及其制备方法的薄膜晶体管。

5. 发明申请

US20050148143A1 Deposition method of insulating layers having low dielectric constant of semiconductor device, a thin film transistor substrate using the same and a method of manufacturing the same 有权
标题翻译：具有低介电常数的半导体器件的绝缘层的沉积方法，使用其的薄膜晶体管基板及其制造方法
公开(公告)号：US20050148143A1
公开(公告)日：2005-07-07
申请号：US11071544
申请日：2005-03-03
申请人： Sung-Hoon Yang , Wan-Shick Hong , Kwan-Wook Jung
发明人： Sung-Hoon Yang , Wan-Shick Hong , Kwan-Wook Jung
IPC分类号： G02F1/1368 , C23C16/30 , C23C16/42 , G02F1/1362 , H01L21/205 , H01L21/312 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/32 , H01L29/786 , H01L51/56
CPC分类号： G02F1/136227 , C23C16/30 , G02F2001/136222 , H01L27/12 , H01L27/1248 , H01L27/1288 , H01L27/3244 , H01L29/458 , H01L29/4908 , H01L51/56
摘要： The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.
摘要翻译：本发明涉及一种用于气相沉积低介电绝缘膜的方法，使用其的薄膜晶体管及其制备方法，更具体地涉及可以显着改善蒸气的低介电绝缘膜的气相沉积方法同时保持低介电绝缘膜的性能，从而解决了寄生电容问题，以实现高开口率结构，并且通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时可以减少处理时间，以形成用于半导体器件的保护膜。本发明还涉及使用该方法及其制备方法的薄膜晶体管。

6. 发明授权

US07902549B2 Deposition method of insulating layers having low dielectric constant of semiconductor device, a thin film transistor substrate using the same and a method of manufacturing the same 有权
标题翻译：具有低介电常数的半导体器件的绝缘层的沉积方法，使用其的薄膜晶体管基板及其制造方法
公开(公告)号：US07902549B2
公开(公告)日：2011-03-08
申请号：US11950476
申请日：2007-12-05
申请人： Sung-Hoon Yang , Wan-Shick Hong , Kwan-Wook Jung
发明人： Sung-Hoon Yang , Wan-Shick Hong , Kwan-Wook Jung
IPC分类号： H01L31/036
CPC分类号： G02F1/136227 , C23C16/30 , G02F2001/136222 , H01L27/12 , H01L27/1248 , H01L27/1288 , H01L27/3244 , H01L29/458 , H01L29/4908 , H01L51/56
摘要： The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.
摘要翻译：本发明涉及一种用于气相沉积低介电绝缘膜的方法，使用其的薄膜晶体管及其制备方法，更具体地涉及可以显着改善蒸气的低介电绝缘膜的气相沉积方法同时保持低介电绝缘膜的性能，从而解决了寄生电容问题，以实现高开口率结构，并且通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时可以减少处理时间，以形成用于半导体器件的保护膜。本发明还涉及使用该方法及其制备方法的薄膜晶体管。

7. 发明授权

US06933568B2 Deposition method of insulating layers having low dielectric constant of semiconductor device, a thin film transistor substrate using the same and a method of manufacturing the same 有权
标题翻译：具有低介电常数的半导体器件的绝缘层的沉积方法，使用其的薄膜晶体管基板及其制造方法
公开(公告)号：US06933568B2
公开(公告)日：2005-08-23
申请号：US10150482
申请日：2002-05-17
申请人： Sung-Hoon Yang , Wan-Shick Hong , Kwan-Wook Jung
发明人： Sung-Hoon Yang , Wan-Shick Hong , Kwan-Wook Jung
IPC分类号： G02F1/1368 , C23C16/30 , C23C16/42 , G02F1/1362 , H01L21/205 , H01L21/312 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/32 , H01L29/786 , H01L51/56 , H01L27/01 , H01L29/76 , H01L31/0288 , H01L31/112
CPC分类号： G02F1/136227 , C23C16/30 , G02F2001/136222 , H01L27/12 , H01L27/1248 , H01L27/1288 , H01L27/3244 , H01L29/458 , H01L29/4908 , H01L51/56
摘要： The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of lowdielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.
摘要翻译：本发明涉及一种用于气相沉积低介电绝缘膜的方法，使用该方法的薄膜晶体管及其制备方法，更具体地涉及一种能够显着改善气相沉积的低电绝缘膜的气相沉积方法同时保持低介电绝缘膜的性能，从而解决了寄生电容问题，以实现高开口率结构，并且通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时可以减少处理时间，以形成保护薄膜用于半导体器件。本发明还涉及使用该方法及其制备方法的薄膜晶体管。

8. 发明授权

US07061015B2 Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion 有权
标题翻译：半导体器件的接触部分和包括该接触部分的显示器件的薄膜晶体管阵列面板
公开(公告)号：US07061015B2
公开(公告)日：2006-06-13
申请号：US10466299
申请日：2002-10-08
申请人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
发明人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L21/76802 , H01L21/76804 , H01L23/53295 , H01L27/12 , H01L27/1244 , H01L27/1248 , H01L2924/0002 , H01L2924/00
摘要： A gate wire is formed on a substrate. Next, after forming a gate insulating film, a semiconductor layer and an ohmic contact layer subsequently are formed thereon. Next, a data wire is formed. Next, a passivation layer and an organic insulating film are deposited, and patterned to form contact holes for exposing the drain electrode, the gate pad and the data pad, respectively. Here, the organic insulating film around the contact holes is formed thinner than that in the other portions. Next, the organic insulating film around the contact holes is removed by an ashing process to expose the borderline of the passivation layer in the contact holes, thereby removing an under-cut. Then, a pixel electrode, an assistant gate pad and an assistant data pad respectively connected to the drain electrode, the gate pad and the data pad are formed.
摘要翻译：在基板上形成栅极线。接下来，在形成栅极绝缘膜之后，随后形成半导体层和欧姆接触层。接下来，形成数据线。接下来，沉积钝化层和有机绝缘膜，并图案化以形成用于分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。这里，接触孔周围的有机绝缘膜的厚度比其他部分薄。接下来，通过灰化处理去除接触孔周围的有机绝缘膜，以暴露接触孔中的钝化层的边界线，从而去除下切。然后，形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，辅助栅极焊盘和辅助数据焊盘。

9. 发明申请

US20060231846A1 Thin film transistor array panel for liquid crystal display 有权
标题翻译：用于液晶显示的薄膜晶体管阵列面板
公开(公告)号：US20060231846A1
公开(公告)日：2006-10-19
申请号：US11455367
申请日：2006-06-19
申请人： Mun-Pyo Hong , Wan-Shick Hong , Sang-Il Kim , Soo-Guy Rho , Jin-Kyu Kang , Snag-Gab Kim
发明人： Mun-Pyo Hong , Wan-Shick Hong , Sang-Il Kim , Soo-Guy Rho , Jin-Kyu Kang , Snag-Gab Kim
IPC分类号： H01L33/00
CPC分类号： G02F1/136227 , G02F1/136209 , G02F1/136286 , G02F2001/136222 , H01L27/12 , H01L27/1255 , H01L27/1288 , H01L29/42384 , H01L29/4908
摘要： A black matrix having an opening at pixels of a matrix array in a display area, a common wire including common pads and common signal lines, and gate pads in a peripheral area, and an alignment key in outer area to align interlayer thin films are formed on an insulating substrate. Red, blue and green color filters the edge of which overlap the black matrix are formed at the pixels on the insulating substrate, and an organic insulating layer covering the black matrix and the color filters and having a contact hole exposing the gate pad is formed thereon. A gate wire including a gate line connected to the gate pad through the contact hole and a gate electrode connected to the gate line is formed on the organic insulating layer, and a gate insulating layer covering the gate wire is formed on the organic insulating layer. A semiconductor pattern and ohmic contact layers are sequentially formed on the gate insulating layer of the gate electrode. A data wire including a source electrode and a drain electrode that are made of a same layer on the ohmic contact layers and separated from each other, and a data line connected to the source electrode and defining the pixels of a matrix array by crossing the gate line is formed on the gate insulating layer. A passivation layer covering the data wire and having contact holes exposing the gate pad and the data pad is formed, and a pixel wire including a pixel electrode, a redundant gate pad, a redundant data pad that are respectively connected to the drain electrode, the gate pad and the data pad through the contact holes.
摘要翻译：形成在显示区域中具有矩阵阵列的像素的开口的黑矩阵，包括公共焊盘和公共信号线的公共线，以及外围区域中的栅极焊盘以及外部区域中的对准键来对准层间薄膜在绝缘基板上。在绝缘基板上的像素处形成与黑矩阵重叠的边缘的红色，蓝色和绿色滤色片，并且在其上形成覆盖黑矩阵和滤色器并且具有暴露栅极接触孔的接触孔的有机绝缘层。在有机绝缘层上形成包括通过接触孔连接到栅极焊盘的栅极线和连接到栅极线的栅极的栅极线，并且在有机绝缘层上形成覆盖栅极线的栅极绝缘层。半导体图案和欧姆接触层依次形成在栅电极的栅极绝缘层上。一种数据线，包括在欧姆接触层上由相同层制成并彼此分离的源电极和漏电极，以及连接到源电极并通过跨越栅极定义矩阵阵列的像素的数据线线形成在栅极绝缘层上。形成覆盖数据线并具有露出栅极焊盘和数据焊盘的接触孔的钝化层，并且包括分别连接到漏电极的像素电极，冗余栅极焊盘，冗余数据焊盘的像素线，栅极焊盘和数据焊盘通过接触孔。

10. 发明申请

US20060209223A1 Thin film transistor array substrate using low dielectric insulating layer and method of fabricating the same 有权
公开(公告)号：US20060209223A1
公开(公告)日：2006-09-21
申请号：US11436073
申请日：2006-05-17
申请人： Joo-Hoo Choi , Wan-Shick Hong , Dae-Jin Kwon , Kwan-Wook Jung , Sang-Gab Kim , Kyu-Ha Jung
发明人： Joo-Hoo Choi , Wan-Shick Hong , Dae-Jin Kwon , Kwan-Wook Jung , Sang-Gab Kim , Kyu-Ha Jung
IPC分类号： G02F1/136
CPC分类号： H01L29/66765 , G02F1/136227 , G02F2001/133357 , G02F2001/136236 , H01L27/12 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array substrate is provided. The substrate includes an insulating substrate, a first signal line formed on the insulating substrate, a first insulating layer formed on the first signal line, a second signal line formed on the first insulating layer while crossing over the first signal line, a thin film transistor connected to the first and the second signal lines, a second insulating layer formed on the thin film transistor, the second insulating layer having dielectric constant about 4.0 or less, and the second insulating layer having a first contact hole exposing a predetermined electrode of the thin film transistor, and a first pixel electrode formed on the second insulating layer while being connected to the predetermined electrode of the thin film transistor through the first contact hole.

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