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1. 发明申请

US20130020649A1 NITRIDE ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：氮化物电子器件及其制造方法
公开(公告)号：US20130020649A1
公开(公告)日：2013-01-24
申请号：US13548522
申请日：2012-07-13
申请人： Sung Bum BAE , Eun Soo NAM , Jae Kyoung MUN , Sung Bock KIM , Hae Cheon KIM , Chull Won JU , Sang Choon KO , Jong-Won LIM , Ho Kyun AHN , Woo Jin CHANG , Young Rak PARK
发明人： Sung Bum BAE , Eun Soo NAM , Jae Kyoung MUN , Sung Bock KIM , Hae Cheon KIM , Chull Won JU , Sang Choon KO , Jong-Won LIM , Ho Kyun AHN , Woo Jin CHANG , Young Rak PARK
IPC分类号： H01L27/088 , H01L21/20 , H01L27/08
CPC分类号： H01L29/66446 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L21/8252 , H01L27/0605 , H01L27/0883
摘要： The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
摘要翻译：本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可以通过再生技术在同一衬底上实现各种氮化物一体化结构（用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG）。

2. 发明申请

US20130069173A1 POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20130069173A1
公开(公告)日：2013-03-21
申请号：US13592560
申请日：2012-08-23
申请人： Woo Jin CHANG , Jong Won LIM , Ho Kyun AHN , Sang Choon KO , Sung Bum BAE , Chull Won JU , Young Rak PARK , Jae Kyoung MUN , Eun Soo NAM
发明人： Woo Jin CHANG , Jong Won LIM , Ho Kyun AHN , Sang Choon KO , Sung Bum BAE , Chull Won JU , Young Rak PARK , Jae Kyoung MUN , Eun Soo NAM
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66901 , H01L29/2003 , H01L29/401 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode;and a metal configured to connect the field plate and the source electrode.
摘要翻译：公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

3. 发明申请

US20090146184A1 SEMICONDUCTOR DEVICE WITH T-GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：具有T型电极的半导体器件及其制造方法
公开(公告)号：US20090146184A1
公开(公告)日：2009-06-11
申请号：US12122982
申请日：2008-05-19
申请人： Jong Won LIM , Ho Kyun AHN , Hong Gu JI , Woo Jin CHANG , Jae Kyoung MUN , Hae Cheon KIM , Hyun Kyu YU
发明人： Jong Won LIM , Ho Kyun AHN , Hong Gu JI , Woo Jin CHANG , Jae Kyoung MUN , Hae Cheon KIM , Hyun Kyu YU
IPC分类号： H01L29/812 , H01L21/335
CPC分类号： H01L29/778 , H01L29/20 , H01L29/42316 , H01L29/66462
摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.
摘要翻译：提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

4. 发明申请

US20090170250A1 TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件的晶体管及其制造方法
公开(公告)号：US20090170250A1
公开(公告)日：2009-07-02
申请号：US12396614
申请日：2009-03-03
申请人： Jae Kyoung MUN , Jong Won LIM , Woo Jin CHANG , Hong Gu JI , Ho Kyun AHN , Hae Cheon KIM
发明人： Jae Kyoung MUN , Jong Won LIM , Woo Jin CHANG , Hong Gu JI , Ho Kyun AHN , Hae Cheon KIM
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

5. 发明申请

US20080129427A1 HIGH-ISOLATION SWITCHING DEVICE FOR MILLIMETER-WAVE BAND CONTROL CIRCUIT 有权
标题翻译：用于微波波段控制电路的高隔离开关装置
公开(公告)号：US20080129427A1
公开(公告)日：2008-06-05
申请号：US11928410
申请日：2007-10-30
申请人： Jae Kyoung MUN , Hae Cheon Kim , Dong Young Kim , Jong Won Lim , Ho Kyun Ahn , Hyun Kyu Yu
发明人： Jae Kyoung MUN , Hae Cheon Kim , Dong Young Kim , Jong Won Lim , Ho Kyun Ahn , Hyun Kyu Yu
IPC分类号： H01P1/10
CPC分类号： H01P1/15
摘要： Provided is a high-isolation switching device for a millimeter-wave band control circuit. By optimizing a cell structure to improve the isolation of an off-state without deteriorating the insertion loss of an on-state, it is possible to implement a high-isolation switching device useful in the design and manufacture of a millimeter-wave band control circuit such as a phase shifter or digital attenuator using switching characteristics. In addition, when a switch microwave monolithic integrated circuit (MMIC) is designed to use the switching device, it is not necessary to use a multi-stage shunt field effect transistor (FET) to improve isolation, nor to dispose an additional λ/4 transformer transmission line, inductor or capacitor near the switching device. Thus, chip size can be reduced, degree of integration can be enhanced, and manufacturing yield can be increased. Consequently, it is possible to reduce manufacturing cost.
摘要翻译：提供了一种用于毫米波段控制电路的高隔离开关装置。通过优化单元结构以改善断开状态的隔离而不会导致导通状态的插入损耗的恶化，可以实现用于设计和制造毫米波段控制电路的高隔离开关装置例如使用开关特性的移相器或数字衰减器。另外，当开关微波单片集成电路（MMIC）被设计为使用开关器件时，不需要使用多级并联场效应晶体管（FET）来改善隔离度，也不需要配置额外的λ/ 4 变压器输电线路，电感器或电容器附近的开关装置。因此，可以降低芯片尺寸，可以提高集成度，并且可以提高制造成品率。因此，可以降低制造成本。

6. 发明申请

US20080251858A1 FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20080251858A1
公开(公告)日：2008-10-16
申请号：US12122805
申请日：2008-05-19
申请人： Ho Kyun AHN , Jong Won LIM , Jae Kyoung MUN , Hong Gu JI , Woo Jin CHANG , Hea Cheon KIM
发明人： Ho Kyun AHN , Jong Won LIM , Jae Kyoung MUN , Hong Gu JI , Woo Jin CHANG , Hea Cheon KIM
IPC分类号： H01L29/49
CPC分类号： H01L29/812 , H01L29/42316 , H01L29/66462 , H01L29/66856 , H01L29/778
摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.
摘要翻译：提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

7. 发明申请

US20130134554A1 VERTICAL CAPACITORS AND METHODS OF FORMING THE SAME 有权
标题翻译：垂直电容器及其形成方法
公开(公告)号：US20130134554A1
公开(公告)日：2013-05-30
申请号：US13618873
申请日：2012-09-14
申请人： Seong-il KIM , Sang-Heung LEE , Jong-Won LIM , Hyung Sup YOON , Jongmin LEE , Byoung-Gue MIN , Jae Kyoung MUN , Eun Soo NAM
发明人： Seong-il KIM , Sang-Heung LEE , Jong-Won LIM , Hyung Sup YOON , Jongmin LEE , Byoung-Gue MIN , Jae Kyoung MUN , Eun Soo NAM
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/91 , H01L23/481 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.
摘要翻译：提供垂直电容器及其形成方法。垂直电容器的形成可以包括在衬底的顶表面上形成输入和输出电极，蚀刻衬底的底表面以形成通孔电极，然后在通孔电极之间形成电介质层。结果，可以在基板的小区域中提供具有高电容的垂直电容器。

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