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1. 发明申请

US20130020649A1 NITRIDE ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：氮化物电子器件及其制造方法
公开(公告)号：US20130020649A1
公开(公告)日：2013-01-24
申请号：US13548522
申请日：2012-07-13
申请人： Sung Bum BAE , Eun Soo NAM , Jae Kyoung MUN , Sung Bock KIM , Hae Cheon KIM , Chull Won JU , Sang Choon KO , Jong-Won LIM , Ho Kyun AHN , Woo Jin CHANG , Young Rak PARK
发明人： Sung Bum BAE , Eun Soo NAM , Jae Kyoung MUN , Sung Bock KIM , Hae Cheon KIM , Chull Won JU , Sang Choon KO , Jong-Won LIM , Ho Kyun AHN , Woo Jin CHANG , Young Rak PARK
IPC分类号： H01L27/088 , H01L21/20 , H01L27/08
CPC分类号： H01L29/66446 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L21/8252 , H01L27/0605 , H01L27/0883
摘要： The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
摘要翻译：本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可以通过再生技术在同一衬底上实现各种氮化物一体化结构（用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG）。

2. 发明申请

US20090170250A1 TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件的晶体管及其制造方法
公开(公告)号：US20090170250A1
公开(公告)日：2009-07-02
申请号：US12396614
申请日：2009-03-03
申请人： Jae Kyoung MUN , Jong Won LIM , Woo Jin CHANG , Hong Gu JI , Ho Kyun AHN , Hae Cheon KIM
发明人： Jae Kyoung MUN , Jong Won LIM , Woo Jin CHANG , Hong Gu JI , Ho Kyun AHN , Hae Cheon KIM
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

3. 发明申请

US20090146184A1 SEMICONDUCTOR DEVICE WITH T-GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：具有T型电极的半导体器件及其制造方法
公开(公告)号：US20090146184A1
公开(公告)日：2009-06-11
申请号：US12122982
申请日：2008-05-19
申请人： Jong Won LIM , Ho Kyun AHN , Hong Gu JI , Woo Jin CHANG , Jae Kyoung MUN , Hae Cheon KIM , Hyun Kyu YU
发明人： Jong Won LIM , Ho Kyun AHN , Hong Gu JI , Woo Jin CHANG , Jae Kyoung MUN , Hae Cheon KIM , Hyun Kyu YU
IPC分类号： H01L29/812 , H01L21/335
CPC分类号： H01L29/778 , H01L29/20 , H01L29/42316 , H01L29/66462
摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.
摘要翻译：提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

4. 发明申请

US20110037521A1 POWER AMPLIFIER HAVING DEPLETION MODE HIGH ELECTRON MOBILITY TRANSISTOR 有权
标题翻译：具有分离模式高电子移动晶体管的功率放大器
公开(公告)号：US20110037521A1
公开(公告)日：2011-02-17
申请号：US12855055
申请日：2010-08-12
申请人： Dong Min KANG , Hong Gu JI , Hokyun AHN , Jong-Won LIM , Woojin CHANG , Sang-Heung LEE , Dong-Young KIM , Hae Cheon KIM
发明人： Dong Min KANG , Hong Gu JI , Hokyun AHN , Jong-Won LIM , Woojin CHANG , Sang-Heung LEE , Dong-Young KIM , Hae Cheon KIM
IPC分类号： H03F3/04
CPC分类号： H03F3/24 , H03F1/565 , H03F3/195 , H03F2200/222
摘要： Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.
摘要翻译：提供了一种功率放大器，包括：耗尽型高电子迁移率晶体管（D模式HEMT），被配置为放大输入到栅极端子的信号，并通过漏极端子输出放大的信号; 输入匹配电路，被配置为使所述栅极端子串联接地; 以及连接在漏极端子和地之间的DC偏置电路。通过上述配置，HEMT可以仅由单个DC偏置电路偏压而没有任何偏置装置来提供负电压。此外，可以通过并联电感器和扼流电感器在各种工作频带中提供优异的匹配特性。

5. 发明申请

US20080136566A1 SIGNAL TRANSMISSION LINE FOR MILLIMETER-WAVE BAND 有权
标题翻译：信号波导信号线
公开(公告)号：US20080136566A1
公开(公告)日：2008-06-12
申请号：US11872026
申请日：2007-10-14
申请人： Ho Young KIM , Hae Cheon KIM , Hyun Kyu YU , Young Jun CHONG
发明人： Ho Young KIM , Hae Cheon KIM , Hyun Kyu YU , Young Jun CHONG
IPC分类号： H01P3/08
CPC分类号： H01P3/00
摘要： Provided is a signal transmission line for a millimeter-wave band. The signal transmission line includes: a dielectric substrate; an input line formed on the dielectric substrate; a pair of serial transmission lines formed on the dielectric substrate, the serial transmission lines being branched at, separated from, and electromagnetically connected in series with one end of the input line; a pair of parallel transmission lines respectively formed on the dielectric substrate at both sides of the input line and the serial transmission lines, and having both ends separated from and electromagnetically connected in parallel with one end of each of the input line and the serial transmission lines; and a pair of wires electrically connected between the other ends of the parallel transmission lines and a connection pad of a monolithic microwave integrated circuit (MMIC). An electrical signal of about 57 to 63 GHz generated from a monolithic microwave integrated circuit (MMIC) can be efficiently transferred.
摘要翻译：提供了一种用于毫米波段的信号传输线。信号传输线包括：电介质基片; 形成在电介质基板上的输入线; 形成在电介质基板上的一对串行传输线，串联传输线与输入线的一端分离并分离并与之电磁连接; 分别在输入线和串行传输线的两侧形成在电介质基板上的一对平行传输线，并且其两端与输入线和串行传输线的一端分开并与之并联电磁连接 ; 以及电连接在并行传输线的另一端之间的一对电线和单片微波集成电路（MMIC）的连接焊盘。可以有效地传送从单片微波集成电路（MMIC）产生的约57至63GHz的电信号。

6. 发明申请

US20080132194A1 SUB-HARMONIC MIXER 失效
标题翻译：辅助混合器
公开(公告)号：US20080132194A1
公开(公告)日：2008-06-05
申请号：US11946315
申请日：2007-11-28
申请人： Hong Gu JI , Hae Cheon KIM , Hyun Kyu YU
发明人： Hong Gu JI , Hae Cheon KIM , Hyun Kyu YU
IPC分类号： H04B1/26
CPC分类号： H03D7/1425 , H03D7/1433 , H03D7/1441 , H03D7/1475 , H03D2200/0043
摘要： A sub-harmonic mixer is provided, which includes: a mixer core having first and second transistors performing switching operations in response to a local oscillator (LO) signal and a radio frequency (RF) signal; a power source applying bias maximizing nonlinearity of a transistor included in the mixer core; an RF port applying an RF signal to the mixer core; an LO port applying an LO signal to the mixer core; and first and second phase delay circuits in which the RF signals applied to the first and second transistors have a 180-degree phase difference.
摘要翻译：提供了一种亚谐波混频器，其包括：具有第一和第二晶体管的混频器核，其响应于本地振荡器（LO）信号和射频（RF）信号执行切换操作; 施加偏置最大化混合器核心中包括的晶体管的非线性的电源; 将RF信号施加到混频器核心的RF端口; LO端口将LO信号施加到混频器核心; 以及施加到第一和第二晶体管的RF信号具有180度相位差的第一和第二相位延迟电路。

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