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1. 发明授权

US06340615B1 Method of forming a trench capacitor DRAM cell 失效
标题翻译：形成沟槽电容器DRAM单元的方法
公开(公告)号：US06340615B1
公开(公告)日：2002-01-22
申请号：US09466605
申请日：1999-12-17
申请人： Sundar K. Iyer , Rama Divakaruni , Herbert L. Ho , Subramanian Iyer , Babar A. Khan
发明人： Sundar K. Iyer , Rama Divakaruni , Herbert L. Ho , Subramanian Iyer , Babar A. Khan
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A method of connecting a trench capacitor in a dynamic random access memory (DRAM) cell. First, trenches are formed in a silicon substrate using a masking layer including a pad nitride layer on a pad oxide layer. Trench capacitors are formed in the trenches. A buried strap is formed in each trench on the capacitor. The nitride pad layer is pulled back from the trench openings, exposing the pad oxide layer and any strap material that may have replaced the pad oxide layer around the trenches. The straps and trench sidewalls are doped to form a resistive connection. During a subsequent shallow trench isolation (STI) process, which involves an oxidation step, the exposed strap material on the surface of the silicon surface layer forms oxide unrestrained by pad nitride without stressing the silicon substrate.
摘要翻译：一种在动态随机存取存储器（DRAM）单元中连接沟槽电容器的方法。首先，在硅衬底中使用在衬垫氧化物层上包括衬垫氮化物层的掩模层形成沟槽。沟槽电容器形成在沟槽中。在电容器的每个沟槽中形成掩埋带。氮化物衬垫层从沟槽开口被拉回，暴露衬垫氧化物层和可能已经替换衬垫氧化物层的任何带材料围绕沟槽。带和沟槽侧壁被掺杂以形成电阻连接。在随后的涉及氧化步骤的浅沟槽隔离（STI）工艺中，硅表面层表面上的暴露的带材料形成不受衬垫氮化物束缚的氧化物，而不会压迫硅衬底。

2. 发明授权

US06323535B1 Electrical fuses employing reverse biasing to enhance programming 失效
标题翻译：采用反向偏置的电气保险丝来加强编程
公开(公告)号：US06323535B1
公开(公告)日：2001-11-27
申请号：US09595764
申请日：2000-06-16
申请人： Sundar K. Iyer , Peter Smeys , Chandrasekhar Narayan , Subramanian Iyer , Axel Brintzinger
发明人： Sundar K. Iyer , Peter Smeys , Chandrasekhar Narayan , Subramanian Iyer , Axel Brintzinger
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.
摘要翻译：根据本发明的用于半导体器件的熔丝包括第一掺杂剂类型的第一掺杂剂类型的阴极和包括第二掺杂剂类型的第二掺杂剂类型的阳极。熔丝连接器连接阴极和阳极并且包括第二掺杂剂类型。熔丝链和阴极在它们之间形成一个结，并且该结被配置为相对于阴极电位和阳极电位被反向偏置。导电层跨越结形成，使得在结处流动的电流被转移到导电层中以增强材料迁移以对熔丝进行编程。

3. 发明授权

US06433404B1 Electrical fuses for semiconductor devices 失效
标题翻译：半导体器件用电熔丝
公开(公告)号：US06433404B1
公开(公告)日：2002-08-13
申请号：US09499495
申请日：2000-02-07
申请人： Sundar K. Iyer , Chandcasekhar Narayan , Axel Brintzinger , Subramanian Iyer
发明人： Sundar K. Iyer , Chandcasekhar Narayan , Axel Brintzinger , Subramanian Iyer
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse for semiconductor devices, in accordance with the present invention, includes a cathode formed from a first material, an anode formed from a second material and a fuse link connecting the cathode and the anode and formed from the second material. The second material is more susceptible to material migration than the first material when the fuse is electrically active such that material migration is enhanced in the second material.
摘要翻译：根据本发明的用于半导体器件的熔断器包括由第一材料形成的阴极，由第二材料形成的阳极和连接阴极和阳极并由第二材料形成的熔丝连接。当熔丝具有电活性时，第二种材料比第一种材料更容易被材料迁移，使得在第二种材料中材料迁移增强。

4. 发明授权

US06972614B2 Circuits associated with fusible elements for establishing and detecting of the states of those elements 失效
标题翻译：与可熔元件相关联的电路，用于建立和检测这些元件的状态
公开(公告)号：US06972614B2
公开(公告)日：2005-12-06
申请号：US10820092
申请日：2004-04-07
申请人： Mark E. Anderson, II , Sundar K. Iyer , Chandrasekara Kothandaraman , Edward P. Maciejewski , George E. Smith, III
发明人： Mark E. Anderson, II , Sundar K. Iyer , Chandrasekara Kothandaraman , Edward P. Maciejewski , George E. Smith, III
IPC分类号： G11C17/16 , G11C17/18 , H01H37/76
CPC分类号： G11C17/16 , G11C17/18
摘要： An identification circuit for establishing and sensing the state of a fusible element used in on chip identification of the chip's type comprising: a circuit establishing control signals for turning the identification circuit on and off; dual paths energized by the control signals generated by the level setting circuit to energize one path through the fusible element to provide a state level and the other path through a reference path which provides a reference voltage level which is distinguishable from both the blown and unblown states of the fusible element; a differential sensing circuit for comparing the reference voltage level to the state level to provide a signal indicating the state of the fusible element; and protection circuitry to protect the circuit during an operation in which the state of the fusible element is set.
摘要翻译：一种识别电路，用于建立和感测用于芯片类型片上识别的可熔元件的状态，包括：建立用于打开和关闭识别电路的控制信号的电路; 通过由电平设置电路产生的控制信号激励的双路径，以激励通过可熔元件的一条路径，以提供状态电平，并且通过参考路径的另一条路径，该参考路径提供可与吹制状态和非吹出状态区分的参考电压电平的易熔元素; 差分感测电路，用于将参考电压电平与状态电平进行比较，以提供指示可熔元件的状态的信号; 以及用于在设置可熔元件的状态的操作期间保护电路的保护电路。

5. 发明授权

US06432760B1 Method and structure to reduce the damage associated with programming electrical fuses 失效
标题翻译：减少与电气保险丝编程相关的损害的方法和结构
公开(公告)号：US06432760B1
公开(公告)日：2002-08-13
申请号：US09751475
申请日：2000-12-28
申请人： Chandrasekharan Kothandaraman , Michael Stetter , Sundar K. Iyer
发明人： Chandrasekharan Kothandaraman , Michael Stetter , Sundar K. Iyer
IPC分类号： H01L218238
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.
摘要翻译：通过形成由多晶硅层和硅化物层构成的栅极堆叠来形成集成电路（IC）结构中的改进的熔丝结构。在形成硅化物层之后，在硅化物层上沉积蚀刻停止氮化硅层。图案化氮化硅层以暴露硅化物层。在钝化的硅化物层上沉积软钝化层。软钝化层具有低热导率，其将能量限制在硅化物层中，使得对熔丝编程所需的电流最小化。软钝化层的固有延展性防止周围层产生裂纹。

6. 发明授权

US06429091B1 Patterned buried insulator 失效
标题翻译：图案埋地绝缘子
公开(公告)号：US06429091B1
公开(公告)日：2002-08-06
申请号：US09733324
申请日：2000-12-08
申请人： Bomy A. Chen , Alexander Hirsch , Sundar K. Iyer , Nivo Rovedo , Hsing-Jen Wann , Ying Zhang
发明人： Bomy A. Chen , Alexander Hirsch , Sundar K. Iyer , Nivo Rovedo , Hsing-Jen Wann , Ying Zhang
IPC分类号： H01L2176
CPC分类号： H01L29/0653 , H01L21/7621 , H01L21/76224 , H01L21/7624 , H01L21/823418 , H01L21/823481
摘要： A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.
摘要翻译：在源极和漏极之下形成图案化的掩埋绝缘体，通过在身体区域上形成掩模并在要形成源极和漏极的区域中注入一定量的n或p型离子，然后蚀刻STI并蚀刻出植入区。光氧化之后是STI中的共形氧化物沉积以及蚀刻区域，从而仅在需要时形成掩埋氧化物。

7. 发明授权

US06339228B1 DRAM cell buried strap leakage measurement structure and method 失效
标题翻译： DRAM单元埋地带泄漏测量结构及方法
公开(公告)号：US06339228B1
公开(公告)日：2002-01-15
申请号：US09428598
申请日：1999-10-27
申请人： Sundar K. Iyer , Satya Chakravarti , Subramanian S. Iyer
发明人： Sundar K. Iyer , Satya Chakravarti , Subramanian S. Iyer
IPC分类号： H01L2358
CPC分类号： H01L27/10867 , G11C29/50 , H01L22/34
摘要： A test structure and method for determining DRAM cell leakage. The cell leakage test structure includes a pair of buried strap test structures. Each buried strap test structure includes multiple trench capacitors formed in a silicon body. Each trench capacitor is connected to a trench sidewall diffusion by at least one buried strap. An n-well ring surrounds each buried strap test structure and divides the buried strap test structure into two separate array p-wells, one being a contact area and the other a leakage test area. The contact area includes contacts to the trench capacitor plates for the corresponding buried strap test structure. In one buried strap test structure, a layer of polysilicon, essentially covers the trench capacitors in the leakage test area to block source/drain region formation there. The other of the two buried strap test structures includes polysilicon lines simulating wordlines with source and drain regions form on either side. A buried n-band contacts the n-well rings, essentially forming an isolation tub around each array well. Cell leakage is measured by measuring leakage current in each buried strap test structure, individually, and then extracting individual leakage components from the measured result.
摘要翻译：用于确定DRAM单元泄漏的测试结构和方法。电池泄漏测试结构包括一对掩埋带测试结构。每个掩埋带测试结构包括形成在硅体中的多个沟槽电容器。每个沟槽电容器通过至少一个掩埋带连接到沟槽侧壁扩散。一个n阱环围绕每个掩埋带测试结构，并将掩埋带测试结构划分成两个单独的阵列p阱，一个是接触区域，另一个是泄漏测试区域。接触区域包括与沟槽电容器板的接触，用于相应的掩埋带测试结构。在一个掩埋带测试结构中，一层多晶硅，基本上覆盖了泄漏测试区域中的沟槽电容器，以阻止其中的源极/漏极区域形成。两个掩埋带测试结构中的另一个包括模拟字线的多晶硅线，源极和漏极区域形成在两边。埋置的n波段接触n阱环，基本上在每个阵列周围形成隔离盆。通过单独测量每个掩埋带测试结构中的泄漏电流，然后从测量结果中提取单个泄漏分量来测量电池泄漏。

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