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    • 9. 发明授权
    • Circuit structures and methods with BEOL layer(s) configured to block electromagnetic interference
    • BEOL层的电路结构和方法被配置为阻止电磁干扰
    • US07821110B2
    • 2010-10-26
    • US11747342
    • 2007-05-11
    • Dae Ik KimJonghae KimMoon Ju KimChoongyeun Cho
    • Dae Ik KimJonghae KimMoon Ju KimChoongyeun Cho
    • H01L23/552
    • H01L23/552H01L2924/0002H01L2924/00
    • Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.
    • 提供后端(BEOL)电路结构和方法来阻止外部来源或内部产生的电磁干扰。 一种这样的BEOL电路结构包括支撑一个或多个集成电路的一个或多个半导体衬底以及设置在半导体衬底之上的一个或多个BEOL层。 至少一个BEOL层包括至少部分地由在第一方向和第二方向排列的多个元件至少部分地限定的导电图案。 多个元件的大小和位置在第一和第二方向中的至少一个方向上,以阻止特定波长的电磁干扰通过。 在一个实施方案中,第一BEOL层的第一导电图案使电磁干扰偏振,并且第二BEOL层的第二导电图案阻挡极化的电磁干扰。
    • 10. 发明授权
    • Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer
    • 通过背栅电荷转移将数字集成电路从待机模式转换到主动模式
    • US07791403B2
    • 2010-09-07
    • US12206124
    • 2008-09-08
    • Choongyeun ChoDaeik KimJonghae KimMoon Ju Kim
    • Choongyeun ChoDaeik KimJonghae KimMoon Ju Kim
    • G05F1/10G05F3/02
    • H03K19/0016Y10T29/49002
    • Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.
    • 提供了电路和方法,以便于将数字电路从背栅极偏置待机模式转换到主动模式。 数字电路包括半导体衬底,至少部分地设置在半导体衬底中的一个或多个p型阱中的多个n沟道晶体管,至少部分地设置在半导体中的一个或多个n型阱中的多个p沟道晶体管 基板和背栅控制电路。 背栅控制电路电耦合到p型阱和n型阱,以便于将多个n沟道晶体管和多个p沟道晶体管从背栅极偏置待机模式转换到有源 模式,通过自动将电荷从n型阱转移到p型阱,直到达到阱电压阈值,表明晶体管从背栅极偏置待机模式到活动模式的完成转变。