专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09147656B1 Semiconductor device with improved shielding 有权
标题翻译：半导体器件具有改进的屏蔽
公开(公告)号：US09147656B1
公开(公告)日：2015-09-29
申请号：US14328711
申请日：2014-07-11
申请人： Sumit Varshney , Rishi Bhooshan , Meng Kong Lye , Chetan Verma
发明人： Sumit Varshney , Rishi Bhooshan , Meng Kong Lye , Chetan Verma
IPC分类号： H01L23/495 , H01L23/552 , H01L23/522
CPC分类号： H01L23/49558 , H01L23/49541 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/04042 , H01L2224/32245 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A shielding structure for use with semiconductor devices. The shielding structure has a base with fingers that are sized and shaped to extend within the space between pairs of adjacent leads. The base extends within the space between the die flag and the leads. The shielding structure is further connected to one of the grounded leads.
摘要翻译：一种用于半导体器件的屏蔽结构。屏蔽结构具有带指状物的基座，其尺寸和形状被设计成在相邻引线对之间的空间内延伸。基座在芯片标记和引线之间的空间内延伸。屏蔽结构进一步连接到一个接地引线。

2. 发明授权

US08291368B2 Method for reducing surface area of pad limited semiconductor die layout 有权
标题翻译：减少焊盘限制半导体管芯布局的表面积的方法
公开(公告)号：US08291368B2
公开(公告)日：2012-10-16
申请号：US13020814
申请日：2011-02-04
申请人： Chetan Verma , Sumeet Aggarwal , Meng Kong Lye
发明人： Chetan Verma , Sumeet Aggarwal , Meng Kong Lye
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/40 , H01L24/06 , H01L2224/05553 , H01L2224/49113
摘要： A method for reducing a surface area of a pad limited semiconductor die layout includes choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die. Next, the method performs selecting, from the outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to an external connection pad. The method then performs repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row. After he repositioning there is performed a step of adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row. The method then provides for repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on every one of the outer die pad rows, has been selected by the selecting step.
摘要翻译：一种用于减小焊盘限制半导体管芯布局的表面积的方法包括从半导体管芯上的一组外管芯焊盘行中选择外管芯焊盘行，每个外管芯焊盘排与半导体管芯的边缘相邻。接下来，该方法执行从外管芯焊盘行中选择配置为电连接到外部连接焊盘的管芯焊盘的公共管芯焊盘组。然后，该方法执行将内部焊盘排上的公共管芯焊盘组的子组重新定位，内部焊盘排与外部管芯焊盘排相邻。在重新定位之后，执行调整外部管芯焊盘列中的至少一些剩余焊盘的位置的步骤，从而减小外部管芯焊盘排的总长度。该方法然后提供重复上述步骤，直到通过调整位置的步骤不再进一步减小衬垫限制半导体管芯的表面积，或者直到在每个外管芯焊盘排上的每个公共管芯焊盘组已被通过选择步骤选择。

3. 发明申请

US20120049389A1 BOND PAD FOR SEMICONDUCTOR DIE 有权
公开(公告)号：US20120049389A1
公开(公告)日：2012-03-01
申请号：US12874204
申请日：2010-09-01
申请人： Chetan Verma , Shailesh Kumar , Meng Kong Lye
发明人： Chetan Verma , Shailesh Kumar , Meng Kong Lye
IPC分类号： H01L23/488
CPC分类号： H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/04042 , H01L2224/05644 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area. The first part has an IO pad area that is in alignment with the IO pad areas of the other bond pads in the same row, and the second part has an IO probe area that is in alignment with the IO probe areas of the bond pads in the adjacent row. The L-shaped bond pad does not violate design rules even though a part of the pad extends into the corner keep out area.
摘要翻译：半导体管芯沿着主表面的边缘具有一排接合焊盘。模具的角被指定为保留区域，其设计布局规则禁止可探测的焊盘放置在保留区域中，使得可以在相邻排的焊盘的末端之间保持最小距离（即，沿着相邻边缘的接合垫）。每行的接合焊盘具有彼此对准的IO焊盘区域和彼此对准的IO探针区域。大致L形接合焊盘包括从半导体管芯的边缘向内延伸的第一垂直部分和连接到垂直部分的第二水平部分。 L形接合焊盘可以放置在一行中的最后接合焊盘和拐角保持区域之间，并且L形接合焊盘的第二部分延伸到角落保持区域中。第一部分具有与同一行中的其它接合焊盘的IO焊盘区域对准的IO焊盘区域，并且第二部分具有与焊盘的IO探针区域对准的IO探针区域相邻行。即使垫的一部分延伸到角落保持区域，L形接合垫也不违反设计规则。

4. 发明授权

US08242613B2 Bond pad for semiconductor die 有权
标题翻译：用于半导体管芯的焊盘
公开(公告)号：US08242613B2
公开(公告)日：2012-08-14
申请号：US12874204
申请日：2010-09-01
申请人： Chetan Verma , Shailesh Kumar , Meng Kong Lye
发明人： Chetan Verma , Shailesh Kumar , Meng Kong Lye
IPC分类号： H01L23/488 , H01L23/485 , H01L21/768 , H01L23/48
CPC分类号： H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/04042 , H01L2224/05644 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area. The first part has an IO pad area that is in alignment with the IO pad areas of the other bond pads in the same row, and the second part has an IO probe area that is in alignment with the IO probe areas of the bond pads in the adjacent row. The L-shaped bond pad does not violate design rules even though a part of the pad extends into the corner keep out area.
摘要翻译：半导体管芯沿着主表面的边缘具有一排接合焊盘。模具的角被指定为保留区域，其设计布局规则禁止可探测的焊盘放置在保留区域中，使得可以在相邻排的焊盘的末端之间保持最小距离（即，沿着相邻边缘的接合垫）。每行的接合焊盘具有彼此对准的IO焊盘区域和彼此对准的IO探针区域。大致L形接合焊盘包括从半导体管芯的边缘向内延伸的第一垂直部分和连接到垂直部分的第二水平部分。 L形接合焊盘可以放置在一行中的最后接合焊盘和拐角保持区域之间，并且L形接合焊盘的第二部分延伸到角落保持区域中。第一部分具有与同一行中的其它接合焊盘的IO焊盘区域对准的IO焊盘区域，并且第二部分具有与焊盘的IO探针区域对准的IO探针区域相邻行。即使垫的一部分延伸到角落保持区域，L形接合垫也不违反设计规则。

5. 发明申请

US20160163671A1 INTEGRATED CIRCUIT PACKAGE WITH POWER PLATES 审中-公开
标题翻译：集成电路包与电源板
公开(公告)号：US20160163671A1
公开(公告)日：2016-06-09
申请号：US14559893
申请日：2014-12-03
申请人： SHAILESH KUMAR , Rishi Bhooshan , Chee Seng Foong , Vikas Garg , Navas Khan Oratti Kalandar , Chetan Verma
发明人： SHAILESH KUMAR , Rishi Bhooshan , Chee Seng Foong , Vikas Garg , Navas Khan Oratti Kalandar , Chetan Verma
IPC分类号： H01L23/00 , H01L23/31 , H01L21/56 , H01L23/495
CPC分类号： H01L23/49517 , H01L23/3107 , H01L23/49555 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/03334 , H01L2224/04105 , H01L2224/05005 , H01L2224/05541 , H01L2224/12105 , H01L2224/13124 , H01L2224/16245 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/73207 , H01L2224/73227 , H01L2224/73253 , H01L2224/73265 , H01L2224/92164 , H01L2224/92227 , H01L2924/00014 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A surface-mounted integrated circuit package containing a semiconductor die has at least two conductive plates on its lower surface for contacting power and ground areas of a printed circuit board (PCB). The conductive plates are electrically connected to metal studs encapsulated within the package and which link the plates to the power and ground grids of the semiconductor die. Power and ground can thus be provided to the package with conductive patterns on the PCB that match with the plates. The resistance of the plates is low and hence the IR drop across the die is low. By supplying power directly to the package via the plates, the peripheral package pins that would otherwise have been allocated for power (and ground) are now freed up for signal assignment.
摘要翻译：包含半导体管芯的表面安装集成电路封装在其下表面上具有至少两个导电板，用于接触印刷电路板（PCB）的电源和接地区域。导电板电连接到封装在封装内的金属螺柱，并将板连接到半导体管芯的电源和接地栅极。因此，电源和接地可以在PCB上的与板匹配的导电图案上提供给封装。板的电阻低，因此裸片上的IR降低。通过经由板向封装提供电源，否则将分配给电源（和地）的外围封装引脚现在被释放以进行信号分配。

6. 发明申请

US20150364439A1 SEMICONDUCTOR DEVICE HAVING POWER DISTRIBUTION USING BOND WIRES 有权
标题翻译：具有使用BOND线的功率分配的半导体器件
公开(公告)号：US20150364439A1
公开(公告)日：2015-12-17
申请号：US14302425
申请日：2014-06-12
申请人： Shailesh Kumar , Rishi Bhooshan , Vikas Garg , Chetan Verma , Navas Khan Oratti Kalandar
发明人： Shailesh Kumar , Rishi Bhooshan , Vikas Garg , Chetan Verma , Navas Khan Oratti Kalandar
IPC分类号： H01L23/00
CPC分类号： H01L24/49 , H01L24/48 , H01L2224/05554 , H01L2224/4554 , H01L2224/4813 , H01L2224/4911 , H01L2224/4917 , H01L2924/00014 , H01L2924/30101 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.
摘要翻译：半导体器件使用绝缘接合线来将设备周边上的外围电源和接地焊盘连接到位于器件的集成电路管芯的内部区域上的阵列电源和接地焊盘。电源和接地电压使用垂直通孔从阵列接合焊盘传送到一个或多个对应的内部配电层。接合线连接形成构成网格电网的行的行和列，其减小了半导体器件的IR降。

7. 发明申请

US20150221592A1 SEMICONDUCTOR DEVICE WITH PACKAGE-LEVEL DECOUPLING CAPACITORS FORMED WITH BOND WIRES 审中-公开
标题翻译：具有捆绑线形式的封装级解耦电容器的半导体器件
公开(公告)号：US20150221592A1
公开(公告)日：2015-08-06
申请号：US14170651
申请日：2014-02-03
申请人： Chetan Verma , Rishi Bhooshan , Vikas Garg , Shailesh Kumar , Navas Khan Oratti Kalandar
发明人： Chetan Verma , Rishi Bhooshan , Vikas Garg , Shailesh Kumar , Navas Khan Oratti Kalandar
IPC分类号： H01L23/522 , H01L23/00
CPC分类号： H01L24/49 , H01L23/5223 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/48091 , H01L2224/48101 , H01L2224/4813 , H01L2224/48464 , H01L2224/4903 , H01L2224/49052 , H01L2224/49097 , H01L2224/4911 , H01L2224/49111 , H01L2224/49175 , H01L2224/49431 , H01L2924/00014 , H01L2924/1205 , H01L2924/14 , H01L2924/181 , H01L2924/19104 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A decoupling capacitor (decap) for circuitry (e.g., an I/O interface) in a semiconductor die is formed using one or more pairs of (parallel) bond wires wire-bonded to bond pads on a top surface of the die. Depending on the implementation, the pairs of bond wires may be horizontally or vertically aligned and may be bonded to I/O and/or array bond pads.
摘要翻译：用半导体管芯中的电路（例如，I / O接口）的去耦电容器（decap）是使用一对或多对引线键合到管芯顶表面上的接合焊盘的（平行）接合线形成的。根据实施方式，这对接合线可以是水平或垂直对准的并且可以结合到I / O和/或阵列接合焊盘。

8. 发明授权

US09196598B1 Semiconductor device having power distribution using bond wires 有权
标题翻译：具有使用接合线的配电的半导体装置
公开(公告)号：US09196598B1
公开(公告)日：2015-11-24
申请号：US14302425
申请日：2014-06-12
申请人： Shailesh Kumar , Rishi Bhooshan , Vikas Garg , Chetan Verma , Navas Khan Oratti Kalandar
发明人： Shailesh Kumar , Rishi Bhooshan , Vikas Garg , Chetan Verma , Navas Khan Oratti Kalandar
IPC分类号： H01L23/48 , H01L23/00
CPC分类号： H01L24/49 , H01L24/48 , H01L2224/05554 , H01L2224/4554 , H01L2224/4813 , H01L2224/4911 , H01L2224/4917 , H01L2924/00014 , H01L2924/30101 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.
摘要翻译：半导体器件使用绝缘接合线来将设备周边上的外围电源和接地焊盘连接到位于器件的集成电路管芯的内部区域上的阵列电源和接地焊盘。电源和接地电压使用垂直通孔从阵列接合焊盘传送到一个或多个对应的内部配电层。接合线连接形成构成网格电网的行的行和列，其减小了半导体器件的IR降。

9. 发明授权

US09418873B2 Integrated circuit with on-die decoupling capacitors 有权
标题翻译：带片上去耦电容的集成电路
公开(公告)号：US09418873B2
公开(公告)日：2016-08-16
申请号：US14467039
申请日：2014-08-24
申请人： Shailesh Kumar , Vikas Garg , Sumit Varshney , Chetan Verma
发明人： Shailesh Kumar , Vikas Garg , Sumit Varshney , Chetan Verma
IPC分类号： H01L23/48 , H01L23/12 , H01G2/14 , H01L21/50 , H01L23/522 , H01L23/495
CPC分类号： H01L21/50 , H01L23/49503 , H01L23/49551 , H01L23/5223 , H01L2224/05553 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.
摘要翻译：半导体器件具有在备用高速接口之间共享的片上去耦电容器。电容焊盘连接到去耦电容器，内部连接焊盘分别连接到备用接口。内部连接接合线通过电容焊盘和内部连接焊盘将去耦电容器连接到选定的接口，与将器件连接到器件的外部电触点相同。

10. 发明申请

US20160056099A1 INTEGRATED CIRCUIT WITH ON-DIE DECOUPLING CAPACITORS 有权
标题翻译：集成电路与电路解耦电容器
公开(公告)号：US20160056099A1
公开(公告)日：2016-02-25
申请号：US14467039
申请日：2014-08-24
申请人： Shailesh Kumar , Vikas Garg , Sumit Varshney , Chetan Verma
发明人： Shailesh Kumar , Vikas Garg , Sumit Varshney , Chetan Verma
IPC分类号： H01L23/495 , H01L21/50
CPC分类号： H01L21/50 , H01L23/49503 , H01L23/49551 , H01L23/5223 , H01L2224/05553 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.
摘要翻译：半导体器件具有在备用高速接口之间共享的片上去耦电容器。电容焊盘连接到去耦电容器，内部连接焊盘分别连接到备用接口。内部连接接合线通过电容焊盘和内部连接焊盘将去耦电容器连接到选定的接口，与将器件连接到器件的外部电触点相同。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式