专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090031153A1 Power Management Server for Managing Power Consumption 有权
标题翻译：用于管理功耗的电源管理服务器
公开(公告)号：US20090031153A1
公开(公告)日：2009-01-29
申请号：US12184280
申请日：2008-08-01
申请人： Sumanta K. Bahali , Warren D. Bailey , Jimmy G. Foster, SR. , Gregory D. Sellman
发明人： Sumanta K. Bahali , Warren D. Bailey , Jimmy G. Foster, SR. , Gregory D. Sellman
IPC分类号： G06F1/28
CPC分类号： G06F1/3203 , G06F1/3209
摘要： A power management server and method for managing power consumption is disclosed. According to one embodiment, a power management server data processing system is provided, where the power management server data processing system comprises a power management communication port to communicatively couple the power management server data processing system to a power-managed server data processing system and a system management processor coupled to the power management communication port. In the described embodiment, the system management processor comprises power management logic configured to receive power management data from the power-managed server data processing system, to generate a power management command utilizing the power management data, and to transmit the power management command to the power-managed server data processing system utilizing the power management communication port. Moreover, the power management data of the described embodiment comprises power management capability data.
摘要翻译：公开了一种用于管理功耗的电源管理服务器和方法。根据一个实施例，提供了一种电源管理服务器数据处理系统，其中电源管理服务器数据处理系统包括电源管理通信端口，用于将电力管理服务器数据处理系统通信地耦合到功率管理的服务器数据处理系统和系统管理处理器耦合到电源管理通信端口。在所描述的实施例中，系统管理处理器包括被配置为从功率管理的服务器数据处理系统接收功率管理数据的功率管理逻辑，利用功率管理数据产生功率管理命令，并将功率管理命令发送到功率管理服务器数据处理系统利用电源管理通信端口。此外，所描述的实施例的电源管理数据包括电源管理能力数据。

2. 发明申请

US20110160916A1 Fan speed control of rack devices where sum of device airflows is greater than maximum airflow of rack 有权
标题翻译：机架设备的风扇速度控制，其中设备气流的总和大于机架的最大气流
公开(公告)号：US20110160916A1
公开(公告)日：2011-06-30
申请号：US12647357
申请日：2009-12-24
申请人： Sumanta K. Bahali , Vinod Kamath , Jimmy G. Foster, SR.
发明人： Sumanta K. Bahali , Vinod Kamath , Jimmy G. Foster, SR.
IPC分类号： G05D7/06 , G05D23/19
CPC分类号： G05D23/1934 , H05K7/20736 , H05K7/20836
摘要： Computing devices have fan speeds governing airflows through the computing devices. The rack has a maximum airflow associated with a cooling component for the rack. The computing devices transmit their current airflows. A sum of the current airflows is determined. Where the sum is greater than the maximum airflow, the fan speeds of one or more selected computing devices are decreased. The fan speeds of lower priority computing devices may be reduced before the fan speeds higher priority computing devices are reduced. Fan speed reduction may be achieved in a centralized manner, by employing a centralized management component, or in a decentralized manner, without employing a centralized management component.
摘要翻译：计算设备具有控制通过计算设备的气流的风扇速度。机架具有与机架的冷却组件相关的最大气流。计算设备传送其当前气流。确定当前气流的总和。在总和大于最大气流的情况下，减少一个或多个所选计算装置的风扇速度。降低优先级较高的计算设备的风扇速度可能会在风扇转速较高的优先级计算设备减少之前被降低。可以通过采用集中式管理部件或以分散的方式集中地实现风扇减速，而不采用集中式管理部件。

3. 发明申请

US20090157920A1 Dynamically Allocating Communication Lanes For A Plurality Of Input/Output ('I/O') Adapter Sockets In A Point-To-Point, Serial I/O Expansion Subsystem Of A Computing System 失效
标题翻译：在计算系统的点对点串行I / O扩展子系统中动态分配多个输入/输出（'I / O'）适配器插座的通信通道
公开(公告)号：US20090157920A1
公开(公告)日：2009-06-18
申请号：US11956026
申请日：2007-12-13
申请人： Jimmy G. Foster, SR.
发明人： Jimmy G. Foster, SR.
IPC分类号： G06F13/12
CPC分类号： G06F13/409
摘要： Methods, systems, and products are disclosed for dynamically allocating communication lanes for a plurality of sockets in a point-to-point, serial I/O expansion subsystem of a computing system, the expansion subsystem including an switch that supports a maximum number of enabled communication lanes, each socket having a same form factor, each socket connected to the switch using a same predefined number of communication lanes, that include: identifying, during a boot process for the computing system, each of the sockets in which an adapter is installed; determining, for each installed adapter, a maximum link width for that adapter; and enabling, for each of the sockets in which an adapter is installed, a set of communication lanes for communications between the adapter installed in that socket and the expansion subsystem switch in dependence upon the maximum link width for each adapter and the maximum number of enabled communication lanes supported by the switch.
摘要翻译：公开了用于为计算系统的点对点串行I / O扩展子系统中的多个套接字动态分配通信通道的方法，系统和产品，该扩展子系统包括支持最大数目的启用的交换机通信通道，每个插座具有相同的形状因子，每个插座使用相同的预定数量的通信线路连接到交换机，其包括：在计算系统的引导过程期间识别其中安装了适配器的每个插座 ; 为每个安装的适配器确定该适配器的最大链路宽度; 并且对于安装有适配器的每个插座，根据每个适配器的最大链路宽度和启用的最大数量，为安装在该套接字中的适配器和扩展子系统交换机之间的通信提供一组通信通道交换机支持的通信通道。

4. 发明申请

US20110109381A1 Integrated Circuit Die Stacks With Rotationally Symmetric Vias 有权
标题翻译：具有旋转对称通孔的集成电路模块
公开(公告)号：US20110109381A1
公开(公告)日：2011-05-12
申请号：US12616563
申请日：2009-11-11
申请人： Jimmy G. Foster, SR. , Kyu-Hyoun Kim
发明人： Jimmy G. Foster, SR. , Kyu-Hyoun Kim
IPC分类号： H01L25/00 , H01L25/065 , H01L21/822
CPC分类号： H01L23/5384 , H01L21/822 , H01L25/0657 , H01L2224/16 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555
摘要： An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (TSVs') in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.
摘要翻译：一种集成电路管芯堆叠，其包括安装在衬底上的第一集成电路管芯，所述第一管芯包括由通过所述第一管芯的导电通路组成的通孔（“PTV”），其没有连接到所述第一管芯上的任何电路; 以及第一集成电路管芯，与第一管芯相同，相对于第一管芯旋转并安装在第一管芯上，第一管芯中的PTV将来自衬底的信号线通过第一管芯连接到硅通孔（TSV） '）在由连接到第二管芯上的电子电路的第二管芯的导电通路组成的第二管芯中; 其中TSV和PTV设置在每个相同的管芯上，使得每个相同管芯上的TSV和PTV的位置相对于另一相同管芯上的TSV和PTV旋转对称。

5. 发明申请

US20090164846A1 Fault Injection In Dynamic Random Access Memory Modules For Performing Built-In Self-Tests 有权
标题翻译：用于执行内置自检的动态随机存取存储器模块中的故障注入
公开(公告)号：US20090164846A1
公开(公告)日：2009-06-25
申请号：US11960489
申请日：2007-12-19
申请人： Jimmy G. Foster, SR. , Nickolaus J. Gruendler , Suzanne M. Michelich , Jacques B. Taylor
发明人： Jimmy G. Foster, SR. , Nickolaus J. Gruendler , Suzanne M. Michelich , Jacques B. Taylor
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G11C29/02 , G11C5/04 , G11C11/401 , G11C29/022 , G11C29/024 , G11C29/025 , G11C29/16 , G11C29/44 , G11C29/56008
摘要： Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module.
摘要翻译：动态随机存取存储器（“DRAM”）模块中的故障注入用于执行内置的自检（“BIST”），包括通过共享地址总线在存储器控制器的DRAM模块的模式寄存器中建立注入故障成为DRAM模块的一条或多条信号线，故障特征为故障类型; 由存储器控制器通过数据总线向DRAM模块写入数据，识别特定DRAM模块的数据; 并且响应于接收到所述数据，由所述特定DRAM模块将由故障类型表征的故障注入到所述特定DRAM模块的所述一个或多个信号线中。

6. 发明申请

US20090091186A1 SYSTEM AND METHOD FOR MULTIPLE SENSE POINT VOLTAGE REGULATION 失效
标题翻译：多点感应电压调节系统与方法
公开(公告)号：US20090091186A1
公开(公告)日：2009-04-09
申请号：US11869116
申请日：2007-10-09
申请人： Raymond M. Clemo , Jimmy G. Foster, SR. , Suzanne M. Michelich , Sheldon J. Sigrist , Jacques B. Taylor
发明人： Raymond M. Clemo , Jimmy G. Foster, SR. , Suzanne M. Michelich , Sheldon J. Sigrist , Jacques B. Taylor
IPC分类号： H02J3/14
CPC分类号： H02J1/14 , G06F1/26 , Y10T307/406 , Y10T307/858
摘要： The present invention is a system and method for sensing the voltage at multiple sense points. The present invention acquires optimal feedback from a plurality of sources including those integrated on the same motherboard, for populated or unpopulated connectors and for adapter cards plugged into the connectors, for the purpose of controlling the voltage regulator output. The voltage regulator, connected to a logic system, provides voltage to those connectors needing the voltage.
摘要翻译：本发明是用于感测多个感测点处的电压的系统和方法。为了控制电压调节器输出，本发明从多个源获得包括集成在同一主板上的最佳反馈，对于填充或未填充的连接器以及插入到连接器中的适配卡。连接到逻辑系统的电压调节器为需要电压的那些连接器提供电压。

7. 发明申请

US20130019048A1 Memory Access To A Dual In-line Memory Module Form Factor Flash Memory 有权
标题翻译：存储器访问双列直插式存储器模块形状因子闪存
公开(公告)号：US20130019048A1
公开(公告)日：2013-01-17
申请号：US13183776
申请日：2011-07-15
申请人： Patrick M. Bland , Dhruv M. Desai , Jimmy G. Foster, SR. , Makoto Ono
发明人： Patrick M. Bland , Dhruv M. Desai , Jimmy G. Foster, SR. , Makoto Ono
IPC分类号： G06F12/02
CPC分类号： G06F9/3824 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0868 , G06F12/0891 , G06F2212/1016 , G06F2212/305 , G06F2212/311
摘要： Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.
摘要翻译：提供了用于存储器访问双列直插存储器模块（DIMM）形状因子闪存的方法，装置和计算机程序产品。实施例包括由控制器从处理器通过处理器中的可缓存存储器接收读取请求; 由控制器将读请求传送到DIMM外形闪存; 由控制器轮询DIMM形状因子闪存中的读取队列，直到数据准备好读取请求; 通过控制器将与DIMM读写请求对应的数据从DIMM形状因子闪存复制到控制器中的读取队列; 由控制器在控制器和处理器之间的接口上发送用于可缓存存储器的无效命令; 并且响应于接收到无效命令，由处理器读取存储在控制器中的读取队列中的数据。

8. 发明申请

US20100293410A1 Memory Downsizing In A Computer Memory Subsystem 有权
标题翻译：内存缩减在计算机内存子系统
公开(公告)号：US20100293410A1
公开(公告)日：2010-11-18
申请号：US12465702
申请日：2009-05-14
申请人： Patrick M. Bland , Jimmy G. Foster, SR.
发明人： Patrick M. Bland , Jimmy G. Foster, SR.
IPC分类号： G06F11/22 , G06F11/16 , G06F11/00
CPC分类号： G11C29/08 , G11C5/04 , G11C29/88 , G11C2029/0407
摘要： Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules (‘DIMMs’) and each DIMM capable of on-die termination (‘ODT’). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.
摘要翻译：存储器在计算机存储器子系统中缩小尺寸，子系统包括一个或多个计算机存储器通道，每个通道包括几个双列直插存储器模块（“DIMM”）和每个能够进行片上端接（“ODT”）的DIMM。根据本发明的实施例的存储器小型化包括在由固件模块进行的电源自检（“POST”）的存储器初始化测试期间识别计算机存储器子系统中特定通道的有缺陷的DIMM，并且通过固件模块，有缺陷的DIMM，包括为有缺陷的DIMM启用ODT，而不会禁用任何无故障的DIMM。

9. 发明申请

US20130159687A1 Memory Training Results Corresponding To A Plurality Of Memory Modules 有权
标题翻译：内存培训结果对应于多个内存模块
公开(公告)号：US20130159687A1
公开(公告)日：2013-06-20
申请号：US13332092
申请日：2011-12-20
申请人： William H. Cox, JR. , Jimmy G. Foster, SR. , Sumeet Kochar , Ivan R. Zapata
发明人： William H. Cox, JR. , Jimmy G. Foster, SR. , Sumeet Kochar , Ivan R. Zapata
IPC分类号： G06F15/177
CPC分类号： G06F12/0646 , G06F11/3051 , G11C5/04 , G11C7/1066 , G11C7/1093 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.
摘要翻译：提供了用于改善对应于多个存储器模块的存储器训练结果的方法，装置和计算机程序产品。实施例包括在启动包括多个存储器模块的系统的引导顺序时检测硬件配置变化; 产生多个训练迭代，对应于数据选通（DQS）信号与所述多个存储器模块的数据有效数据（DQ）行窗口的对准的参考训练值; 识别每个训练迭代，为该训练迭代生成的参考训练值内的任何外部值; 从参考训练值中消除所识别的外部值; 基于剩余参考训练值的平均值生成最终参考训练值; 并使用最终参考训练值作为系统引导顺序的DQ-DQS定时值。

10. 发明申请

US20120299640A1 Integrated Circuit Die Stacks Having Initially Identical Dies Personalized With Fuses 有权
标题翻译：具有保险丝个性化的最初相同模具的集成电路模块
公开(公告)号：US20120299640A1
公开(公告)日：2012-11-29
申请号：US13569267
申请日：2012-08-08
申请人： Jimmy G. Foster, SR. , Kyu-Hyoun Kim
发明人： Jimmy G. Foster, SR. , Kyu-Hyoun Kim
IPC分类号： H01H37/76 , H01L21/50 , H01L23/48
CPC分类号： H01L23/481 , H01L23/5256 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.
摘要翻译：集成电路芯片堆叠，其具有安装在基板上的第一裸片，所述第一模具被制造成与具有多个穿通硅通孔（TSV）的第二裸片最初相同，所述第一裸片通过在第一裸片上熔化熔丝而被个性化，先前通过熔断保险丝连接的TSV通过通孔（PTV），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具在第二次死亡时死于TSV。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式