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1. 发明授权

US08347154B2 Use of hashing function to distinguish random and repeat errors in a memory system 有权
标题翻译：使用散列函数来区分存储器系统中的随机和重复错误
公开(公告)号：US08347154B2
公开(公告)日：2013-01-01
申请号：US12887184
申请日：2010-09-21
申请人： Sumanta K. Bahali , Tu T. Dang , Michael C. Elles , Juan Q. Hernandez , Dwayne A. Lowe , Challis L. Purrington , Michael L. Scollard , Ivan R. Zapata
发明人： Sumanta K. Bahali , Tu T. Dang , Michael C. Elles , Juan Q. Hernandez , Dwayne A. Lowe , Challis L. Purrington , Michael L. Scollard , Ivan R. Zapata
IPC分类号： G06F11/00
CPC分类号： G06F11/076 , G06F11/008 , G06F11/073 , G06F11/1048 , G11C29/42 , G11C29/44 , G11C2029/0411
摘要： One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.
摘要翻译：一个实施例提供一种错误检测方法，其中检测存储器模块中的单位错误并将其识别为随机错误或重复错误。每个识别的随机误差和每个识别的在时间间隔中发生的重复误差被计数。响应于识别的随机误差的数量达到随机误差阈值或在预定义间隔期间到达重复误差阈值的多个识别的重复错误而产生警报。重复错误阈值设置为低于随机误差阈值。可以将散列处理应用于每个检测到的错误的存储器地址，以将存储器系统中的错误的位置映射到电子表中的相应位置。

2. 发明申请

US20120072786A1 USE OF HASHING FUNCTION TO DISTINGUISH RANDOM AND REPEAT ERRORS IN A MEMORY SYSTEM 有权
标题翻译：使用散列函数来识别存储系统中的随机和重复错误
公开(公告)号：US20120072786A1
公开(公告)日：2012-03-22
申请号：US12887184
申请日：2010-09-21
申请人： Sumanta K. Bahali , Tu T. Dang , Michael C. Elles , Juan Q. Hernandez , Dwayne A. Lowe , Challis L. Purrington , Michael L. Scollard , Ivan R. Zapata
发明人： Sumanta K. Bahali , Tu T. Dang , Michael C. Elles , Juan Q. Hernandez , Dwayne A. Lowe , Challis L. Purrington , Michael L. Scollard , Ivan R. Zapata
IPC分类号： G11C29/04 , G06F11/00 , G06F11/22
CPC分类号： G06F11/076 , G06F11/008 , G06F11/073 , G06F11/1048 , G11C29/42 , G11C29/44 , G11C2029/0411
摘要： One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.
摘要翻译：一个实施例提供一种错误检测方法，其中检测存储器模块中的单位错误并将其识别为随机错误或重复错误。每个识别的随机误差和每个识别的在时间间隔中发生的重复误差被计数。响应于识别的随机误差的数量达到随机误差阈值或在预定义间隔期间到达重复误差阈值的多个识别的重复错误而产生警报。重复错误阈值设置为低于随机误差阈值。可以将散列处理应用于每个检测到的错误的存储器地址，以将存储器系统中的错误的位置映射到电子表中的相应位置。

3. 发明申请

US20120102367A1 Scalable Prediction Failure Analysis For Memory Used In Modern Computers 审中-公开
标题翻译：现代计算机中使用的内存的可扩展预测失败分析
公开(公告)号：US20120102367A1
公开(公告)日：2012-04-26
申请号：US12912735
申请日：2010-10-26
申请人： Tu T. Dang , Michael C. Elles , Juan Q. Hernandez , Dwayne A. Lowe , Challis L. Purrington
发明人： Tu T. Dang , Michael C. Elles , Juan Q. Hernandez , Dwayne A. Lowe , Challis L. Purrington
IPC分类号： G06F11/00
CPC分类号： G11C29/42 , G06F3/0619 , G06F3/0653 , G06F3/0673 , G06F11/0727 , G06F11/0754 , G06F11/076 , G06F11/079 , G06F11/1048 , G06F2201/81 , G11C29/50004 , G11C2029/0409
摘要： One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system.
摘要翻译：一个实施例提供了一种用于可伸缩预测故障分析的方法。该方法的实施例可以包括在具有至少一个处理器的用户计算机系统上收集用于存储器的存储器信息。此外，该方法包括选择一个或多个存储器相关参数。此外，该方法还包括基于采集和选择来计算用于通过利用存储器信息的一个或多个存储器相关参数中的每一个的可伸缩预测故障分析的单个位错误值。此外，该方法包括基于计算来设置用户计算机系统的单个比特误差值。

4. 发明申请

US20090164852A1 Preemptive Thermal Management For A Computing System Based On Cache Performance 有权
标题翻译：基于缓存性能的计算系统的先发热管理
公开(公告)号：US20090164852A1
公开(公告)日：2009-06-25
申请号：US11960599
申请日：2007-12-19
申请人： Challis L. Purrington , Michael L. Scollard , Victor A. Stankevich , Ivan R. Zapata
发明人： Challis L. Purrington , Michael L. Scollard , Victor A. Stankevich , Ivan R. Zapata
IPC分类号： G06F11/07
CPC分类号： G06F1/206
摘要： Methods, apparatus, and products are disclosed for preemptive thermal management for a computing system based on cache performance, the computing system having a processor, cached computer memory operatively coupled to the processor, and a processor cache operatively coupled to the processor, the processor cache capable of storing a subset of memory contents of the cached computer memory, that include: attempting, by the processor, to retrieve portions of the memory contents of the cached computer memory from the processor cache, resulting in cache misses for the processor cache; tracking, by the processor, cache miss statistics for the processor cache in the computing system, the cache miss statistics describing the cache misses for the processor cache; and administering a thermal management device for the computing system in dependence upon the cache miss statistics, the thermal management device operatively coupled to the processor and capable of managing temperature for the computing system.
摘要翻译：公开了用于基于高速缓存性能的计算系统的先占热管理的方法，装置和产品，所述计算系统具有处理器，可操作地耦合到所述处理器的高速缓存计算机存储器，以及可操作地耦合到所述处理器的处理器高速缓存器能够存储缓存的计算机存储器的存储器内容的子集，其包括：由处理器尝试从处理器高速缓存中检索缓存的计算机存储器的存储器内容的部分，导致处理器高速缓存的高速缓存未命中; 由处理器跟踪计算系统中处理器缓存的高速缓存未命中统计信息，描述处理器高速缓存未命中的高速缓存未命中统计信息; 以及根据所述高速缓存未命中统计管理所述计算系统的热管理装置，所述热管理装置可操作地耦合到所述处理器并能够管理所述计算系统的温度。

5. 发明授权

US07971102B2 Preemptive thermal management for a computing system based on cache performance 有权
标题翻译：基于缓存性能的计算系统的抢先热管理
公开(公告)号：US07971102B2
公开(公告)日：2011-06-28
申请号：US11960599
申请日：2007-12-19
申请人： Challis L. Purrington , Michael L. Scollard , Victor A. Stankevich , Ivan R. Zapata
发明人： Challis L. Purrington , Michael L. Scollard , Victor A. Stankevich , Ivan R. Zapata
IPC分类号： G06F11/00
CPC分类号： G06F1/206
摘要： Methods, apparatus, and products are disclosed for preemptive thermal management for a computing system based on cache performance, the computing system having a processor, cached computer memory operatively coupled to the processor, and a processor cache operatively coupled to the processor, the processor cache capable of storing a subset of memory contents of the cached computer memory, that include: attempting, by the processor, to retrieve portions of the memory contents of the cached computer memory from the processor cache, resulting in cache misses for the processor cache; tracking, by the processor, cache miss statistics for the processor cache in the computing system, the cache miss statistics describing the cache misses for the processor cache; and administering a thermal management device for the computing system in dependence upon the cache miss statistics, the thermal management device operatively coupled to the processor and capable of managing temperature for the computing system.
摘要翻译：公开了用于基于高速缓存性能的计算系统的先占热管理的方法，装置和产品，所述计算系统具有处理器，可操作地耦合到所述处理器的高速缓存计算机存储器，以及可操作地耦合到所述处理器的处理器高速缓存器能够存储缓存的计算机存储器的存储器内容的子集，其包括：由处理器尝试从处理器高速缓存中检索缓存的计算机存储器的存储器内容的部分，导致处理器高速缓存的高速缓存未命中; 由处理器跟踪计算系统中处理器缓存的高速缓存未命中统计信息，描述处理器高速缓存未命中的高速缓存未命中统计信息; 以及根据所述高速缓存未命中统计管理所述计算系统的热管理装置，所述热管理装置可操作地耦合到所述处理器并能够管理所述计算系统的温度。

6. 发明申请

US20090254732A1 Enabling Memory Module Slots In A Computing System After A Repair Action 有权
标题翻译：维修行动后，在计算系统中启用内存模块插槽
公开(公告)号：US20090254732A1
公开(公告)日：2009-10-08
申请号：US11960544
申请日：2008-04-08
申请人： Tu T. Dang , Robert F. Kantner, JR. , Henry G. McMillan , Carl A. Morrell , Challis L. Purrington , Mark W. Williams
发明人： Tu T. Dang , Robert F. Kantner, JR. , Henry G. McMillan , Carl A. Morrell , Challis L. Purrington , Mark W. Williams
IPC分类号： G06F12/00
CPC分类号： G06F13/409 , G06F11/006 , G06F11/073 , G06F11/0793
摘要： Methods, systems, and products are disclosed for enabling memory module slots in a computing system after a repair action, the computing system having a plurality of memory module slots and having at least one memory module installed in one of the memory module slots, that includes: determining, during a boot process for the computing system, whether any of the memory module slots are disabled; and if any of the memory module slots are disabled: retrieving, for each memory module installed in one of the memory module slots, a memory module identifier for that memory module, retrieving, from non-volatile memory of the computing system, previously stored memory module identifiers, determining whether the retrieved memory module identifiers match the previously stored memory module identifiers, and enabling the disabled memory module slots if the retrieved memory module identifiers do not match the previously stored memory module identifiers.
摘要翻译：公开了方法，系统和产品，用于在修复动作之后使计算系统中的存储器模块插槽能够启动，所述计算系统具有多个存储器模块插槽，并且具有安装在存储器模块插槽之一中的至少一个存储器模块，：在所述计算系统的引导过程期间确定是否禁用所述存储器模块插槽; 并且如果任何一个存储器模块插槽被禁用：对于安装在其中一个存储器模块插槽中的每个存储器模块，检索该存储器模块的存储器模块标识符，从计算系统的非易失性存储器检索先前存储的存储器模块标识符，确定所检索的存储器模块标识符是否与先前存储的存储器模块标识符匹配，以及如果所检索的存储器模块标识符与先前存储的存储器模块标识符不匹配，则启用禁用的存储器模块插槽。

7. 发明授权

US07654840B1 DIMM connector and memory system with compensated airflow impedance 有权
标题翻译： DIMM连接器和具有补偿气流阻抗的存储器系统
公开(公告)号：US07654840B1
公开(公告)日：2010-02-02
申请号：US12398289
申请日：2009-03-05
申请人： Ivan R. Zapata , Victor A. Stankevich , Challis L. Purrington , Henry G. McMillan , Brian A. Baker
发明人： Ivan R. Zapata , Victor A. Stankevich , Challis L. Purrington , Henry G. McMillan , Brian A. Baker
IPC分类号： H01R4/60
CPC分类号： H01R13/62988 , H01R12/721
摘要： An embodiment of the present invention is directed to a memory module connector having a pivotable air baffle that controls airflow at the memory module connector. When the memory module connector is occupied by a memory module, the air baffle may rest on an upper edge of the memory module, substantially parallel to the system board and in general alignment with the airflow. When the memory module has been removed, the air baffle may be pivoted downward toward the connector base and into the airflow, to offset the reduction in airflow impedance caused by the removal of the memory module from the memory module connector.
摘要翻译：本发明的一个实施例涉及一种存储器模块连接器，其具有控制存储器模块连接器上的气流的可枢转空气挡板。当存储器模块连接器被存储器模块占用时，空气挡板可以搁置在存储器模块的上边缘上，基本上平行于系统板并且与气流大致对准。当存储器模块已经被移除时，空气挡板可以朝向连接器底座向下枢转并进入气流中，以抵消由存储器模块连接器移除存储器模块引起的气流阻抗的减小。

8. 发明授权

US08006028B2 Enabling memory module slots in a computing system after a repair action 有权
标题翻译：在修复操作后，在计算系统中启用内存模块插槽
公开(公告)号：US08006028B2
公开(公告)日：2011-08-23
申请号：US11960544
申请日：2008-04-08
申请人： Tu T. Dang , Robert F. Kantner, Jr. , Henry G. McMillan , Carl A. Morrell , Challis L. Purrington , Mark W. Williams
发明人： Tu T. Dang , Robert F. Kantner, Jr. , Henry G. McMillan , Carl A. Morrell , Challis L. Purrington , Mark W. Williams
IPC分类号： G06F12/00
CPC分类号： G06F13/409 , G06F11/006 , G06F11/073 , G06F11/0793
摘要： Methods, systems, and products are disclosed for enabling memory module slots in a computing system after a repair action, the computing system having a plurality of memory module slots and having at least one memory module installed in one of the memory module slots, that includes: determining, during a boot process for the computing system, whether any of the memory module slots are disabled; and if any of the memory module slots are disabled: retrieving, for each memory module installed in one of the memory module slots, a memory module identifier for that memory module, retrieving, from non-volatile memory of the computing system, previously stored memory module identifiers, determining whether the retrieved memory module identifiers match the previously stored memory module identifiers, and enabling the disabled memory module slots if the retrieved memory module identifiers do not match the previously stored memory module identifiers.
摘要翻译：公开了方法，系统和产品，用于在修复动作之后使计算系统中的存储器模块插槽能够启动，所述计算系统具有多个存储器模块插槽，并且具有安装在存储器模块插槽之一中的至少一个存储器模块，：在所述计算系统的引导过程期间确定是否禁用所述存储器模块插槽; 并且如果任何一个存储器模块插槽被禁用：对于安装在其中一个存储器模块插槽中的每个存储器模块，检索该存储器模块的存储器模块标识符，从计算系统的非易失性存储器检索先前存储的存储器模块标识符，确定所检索的存储器模块标识符是否与先前存储的存储器模块标识符匹配，以及如果所检索的存储器模块标识符与先前存储的存储器模块标识符不匹配，则启用禁用的存储器模块插槽。

9. 发明授权

US07992030B2 Fall time accelerator circuit 有权
标题翻译：下降时间加速器电路
公开(公告)号：US07992030B2
公开(公告)日：2011-08-02
申请号：US11746102
申请日：2007-05-09
申请人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
发明人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
IPC分类号： G06F1/00
CPC分类号： H03K5/1534 , H03K19/01721
摘要： Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.
摘要翻译：本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

10. 发明申请

US20080278207A1 FALL TIME ACCELERATOR CIRCUIT 有权
标题翻译：落地时间加速器电路
公开(公告)号：US20080278207A1
公开(公告)日：2008-11-13
申请号：US11746102
申请日：2007-05-09
申请人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
发明人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
IPC分类号： H03K5/12
CPC分类号： H03K5/1534 , H03K19/01721
摘要： Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.
摘要翻译：本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

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