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1. 发明授权

US07755966B2 Memory device performing a partial refresh operation based on accessed and/or refreshed memory blocks and method thereof 有权
标题翻译：基于访问和/或刷新的存储器块执行部分刷新操作的存储器件及其方法
公开(公告)号：US07755966B2
公开(公告)日：2010-07-13
申请号：US11975021
申请日：2007-10-17
申请人： Suk-Soo Pyo , Hyun-Taek Jung
发明人： Suk-Soo Pyo , Hyun-Taek Jung
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40622
摘要： The present invention provides a memory device which comprises a memory cell array having a plurality of memory blocks; a memory controller for controlling a refresh operation with respect to the memory blocks; a refresh check bit circuit for storing refresh check bits corresponding to the memory blocks, respectively; a block select control circuit for setting refresh check bits of memory blocks to be refreshed to a checked state according to a first control of the memory controller; a using check bit circuit for storing using check bits corresponding to the memory blocks, respectively; a using check control circuit for setting refresh check bits of memory blocks to which access is requested to a checked state according to a second control of the memory controller; and a partial refresh control circuit for controlling the refresh operation such that memory blocks corresponding to checked using check bits or checked refresh check bits are refreshed according to a third control of the memory controller.
摘要翻译：本发明提供了一种存储器件，其包括具有多个存储器块的存储单元阵列; 用于控制相对于存储块的刷新操作的存储器控制器; 刷新检查位电路，用于分别存储对应于存储块的刷新校验位; 块选择控制电路，用于根据存储器控制器的第一控制将要刷新的存储块的刷新校验位设置为检查状态; 使用校验位电路，分别使用与存储块对应的校验位来存储; 使用检查控制电路，用于根据存储器控制器的第二控制将请求访问的存储块的刷新校验位设置为检查状态; 以及部分刷新控制电路，用于控制刷新操作，使得根据存储器控制器的第三控制刷新与使用校验位或检查刷新校验位检查的对应的存储器块。

2. 发明授权

US08208327B2 Semiconductor memory device and data read method thereof 有权
标题翻译：半导体存储器件及其数据读取方法
公开(公告)号：US08208327B2
公开(公告)日：2012-06-26
申请号：US12794033
申请日：2010-06-04
申请人： Suk-Soo Pyo
发明人： Suk-Soo Pyo
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/065 , G11C7/08 , G11C7/12 , G11C11/4091 , G11C2207/002 , G11C2207/005
摘要： A semiconductor memory device includes a first bitline pair equalized to a first voltage level by a first equalizer circuit, a second bitline pair equalized to a second voltage level by a second equalizer circuit, an isolation circuit disposed between the first bitline pair and the second bitline pair, the isolation unit configured to electrically connect or isolate the first bitline pair to or from the second bitline pair, and a sense amplifier electrically connected to the second bitline pair, the sense amplifier configured to sense a voltage difference of the second bitline pair, wherein the isolation circuit isolates one of the connections between the first bitline pair and the second bitline pair while the sense amplifier senses the voltage difference of the second bitline pair.
摘要翻译：半导体存储器件包括由第一均衡器电路等于第一电压电平的第一位线对，由第二均衡器电路等于第二电压电平的第二位线对，设置在第一位线对和第二位线之间的隔离电路所述隔离单元被配置为将所述第一位线对电连接到所述第二位线对或从所述第二位线对隔离，以及电连接到所述第二位线对的读出放大器，所述读出放大器被配置为感测所述第二位线对的电压差，其中所述隔离电路隔离所述第一位线对和所述第二位线对之间的连接中的一个，同时所述读出放大器感测所述第二位线对的电压差。

3. 发明申请

US20080175079A1 Test scheme for fuse circuit 审中-公开
标题翻译：保险丝电路测试方案
公开(公告)号：US20080175079A1
公开(公告)日：2008-07-24
申请号：US12008468
申请日：2008-01-11
申请人： Soon-Keun Jeon , Se-Hyun Hwang , Suk-Soo Pyo
发明人： Soon-Keun Jeon , Se-Hyun Hwang , Suk-Soo Pyo
IPC分类号： G11C29/00 , G11C7/00 , G11C17/18
CPC分类号： G11C29/02 , G11C29/027 , G11C29/846
摘要： Provided is an apparatus and a method for testing an electrical fuse. In accordance therewith: a first test is performed on a plurality of memory cells arranged with a plurality of rows and a plurality of columns; a line related to a defective cell is repaired with a redundant line by using an electrical fuse; data outputted from the redundant line is set with a predetermined value; performing a second test on the plurality of memory cells; and a determination is made of whether or not data outputted from the line related to a defective cell has the predetermined value.
摘要翻译：提供了一种用于测试电熔丝的装置和方法。与此相对应：对多行和多列排列的多个存储单元执行第一测试; 通过使用电熔丝用冗余线修复与缺陷电池相关的线; 从冗余线输出的数据被设定为预定值; 对所述多个存储器单元执行第二测试; 并且确定从与缺陷单元相关的行输出的数据是否具有预定值。

4. 发明授权

US07187608B2 System and method for controlling the access and refresh of a memory 有权
标题翻译：用于控制存储器的访问和刷新的系统和方法
公开(公告)号：US07187608B2
公开(公告)日：2007-03-06
申请号：US11193805
申请日：2005-07-28
申请人： Min-Yeol Ha , Suk-Soo Pyo , Hyun-Taek Jung
发明人： Min-Yeol Ha , Suk-Soo Pyo , Hyun-Taek Jung
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G06F12/0875 , G11C11/406 , G11C11/40603
摘要： The present invention provides a memory and memory control system wherein, except for one case noted below, the main memory gives priority to read or write operations over refresh operations. On the other hand, the cache memory give priority to the refresh operations over read or write operations. The exceptional case is when a memory read signal is received when the cache refresh is enabled and the data in the cache memory is valid. In this exceptional case, the refresh of the cache memory is delayed. During certain read operations the data in the particular memory block is also written to the cache and no write back from the cache is performed. This reduces the number of write back operations and it eliminates a delay due to the refresh operation.
摘要翻译：本发明提供了一种存储器和存储器控制系统，其中除主要存储器之外的一个情况除外，主存储器优先于刷新操作的读或写操作。另一方面，高速缓冲存储器优先于对读或写操作的刷新操作。特殊情况是当启用缓存刷新并且高速缓存中的数据有效时接收到存储器读取信号。在这种特殊情况下，缓存内存的刷新被延迟。在某些读取操作期间，特定存储器块中的数据也被写入高速缓存，并且不执行从缓存的回写。这减少了回写操作的数量，并且消除了由刷新操作引起的延迟。

5. 发明授权

US08644094B2 Semiconductor memory devices including precharge using isolated voltages 有权
标题翻译：半导体存储器件包括使用隔离电压的预充电
公开(公告)号：US08644094B2
公开(公告)日：2014-02-04
申请号：US13477448
申请日：2012-05-22
申请人： Suk-Soo Pyo , Hyun Taek Jung
发明人： Suk-Soo Pyo , Hyun Taek Jung
IPC分类号： G11C7/06
CPC分类号： G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C11/417 , G11C11/419
摘要： A semiconductor memory device includes a memory cell array including a plurality of word lines, a plurality of bit lines including complementary pairs of bit lines, and a plurality of memory cells storing data; a sense amplifier coupled to the memory cell array and configured to sense voltage differences between the complementary pairs of bit lines and amplify the voltage differences; and at least one voltage driver configured to provide either a predetermined voltage or a first power supply voltage to the memory cell array to increase a sensing margin of the semiconductor memory device. The semiconductor memory device increases respective potential differences between complementary pairs of bit lines using a voltage isolated in the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列包括多个字线，多个位线，包括互补的位线对以及存储数据的多个存储单元; 感测放大器，耦合到所述存储单元阵列并且被配置为感测所述互补的位线对之间的电压差，并且放大所述电压差; 以及至少一个电压驱动器，被配置为向存储单元阵列提供预定电压或第一电源电压以增加半导体存储器件的感测裕度。半导体存储器件使用在存储单元阵列中隔离的电压来增加互补的位线对之间的各自的电位差。

6. 发明申请

US20080094931A1 Memory device performing partial refresh operation and method thereof 有权
标题翻译：执行部分刷新操作的存储器件及其方法
公开(公告)号：US20080094931A1
公开(公告)日：2008-04-24
申请号：US11975021
申请日：2007-10-17
申请人： Suk-Soo Pyo , Hyun-Taek Jung
发明人： Suk-Soo Pyo , Hyun-Taek Jung
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40622
摘要： The present invention provides a memory device which comprises a memory cell array having a plurality of memory blocks; a memory controller for controlling a refresh operation with respect to the memory blocks; a refresh check bit storing part for storing refresh check bits corresponding to the memory blocks, respectively; a block select control part for setting refresh check bits of memory blocks to be refreshed to a check state according to a control of the memory controller; a using check bit storing part for storing using check bits corresponding to the memory blocks, respectively; a using check control part for setting refresh check bits of memory blocks access-requested to a check state according to a control of the memory controller; and a partial refresh control part for controlling such that memory blocks corresponding to checked using check bits or refresh check bits according to a control of the memory controller.
摘要翻译：本发明提供了一种存储器件，其包括具有多个存储器块的存储单元阵列; 用于控制相对于存储块的刷新操作的存储器控制器; 刷新检查位存储部分，用于分别存储对应于存储块的刷新校验位; 块选择控制部分，用于根据存储器控制器的控制将要刷新的存储块的刷新校验位设置为校验状态; 使用检查位存储部分，分别使用与所述存储器块相对应的校验位来存储; 使用检查控制部分，用于根据所述存储器控制器的控制来设置访问请求到检查状态的存储器块的刷新检查位; 以及部分刷新控制部分，用于根据存储器控制器的控制来控制使得使用校验位或刷新校验位检查的对应的存储器块。

7. 发明申请

US20170309330A1 RESISTIVE MEMORY DEVICE AND A MEMORY SYSTEM INCLUDING THE SAME 有权
公开(公告)号：US20170309330A1
公开(公告)日：2017-10-26
申请号：US15450831
申请日：2017-03-06
申请人： Suk-Soo Pyo
发明人： Suk-Soo Pyo
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1655 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1693 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0045 , G11C2213/79 , G11C2213/82
摘要： A memory device includes a memory cell array, a read circuit, and a control logic. The memory cell array includes a memory cell having a resistance level that varies depending on data stored therein. The memory cell is connected to a first signal line and a second signal line. The read circuit is configured to read the data. The control logic is configured to precharge a sensing node, connected to the first signal line through a first switching device, and a first node, connected to the second signal line through a second switching device, to different voltage levels during a first period, and develop a voltage of the sensing node based on the resistance level of the memory cell during a second period.

8. 发明申请

US20120300560A1 SEMICONDUCTOR MEMORY DEVICES INCLUDING PRECHARGE USING ISOLATED VOLTAGES 有权
标题翻译：半导体存储器件，其中包括使用隔离电压的前置放大器
公开(公告)号：US20120300560A1
公开(公告)日：2012-11-29
申请号：US13477448
申请日：2012-05-22
申请人： Suk-Soo Pyo , Hyun Taek Jung
发明人： Suk-Soo Pyo , Hyun Taek Jung
IPC分类号： G11C7/06
CPC分类号： G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C11/417 , G11C11/419
摘要： A semiconductor memory device includes a memory cell array including a plurality of word lines, a plurality of bit lines including complementary pairs of bit lines, and a plurality of memory cells storing data; a sense amplifier coupled to the memory cell array and configured to sense voltage differences between the complementary pairs of bit lines and amplify the voltage differences; and at least one voltage driver configured to provide either a predetermined voltage or a first power supply voltage to the memory cell array to increase a sensing margin of the semiconductor memory device. The semiconductor memory device increases respective potential differences between complementary pairs of bit lines using a voltage isolated in the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列包括多个字线，多个位线，包括互补的位线对以及存储数据的多个存储单元; 感测放大器，耦合到所述存储单元阵列并且被配置为感测所述互补的位线对之间的电压差，并且放大所述电压差; 以及至少一个电压驱动器，被配置为向存储单元阵列提供预定电压或第一电源电压以增加半导体存储器件的感测裕度。半导体存储器件使用在存储单元阵列中隔离的电压来增加互补的位线对之间的各自的电位差。

9. 发明授权

US07894282B2 Dynamic random access memory device and method of determining refresh cycle thereof 失效
标题翻译：动态随机存取存储器件及其刷新周期的确定方法
公开(公告)号：US07894282B2
公开(公告)日：2011-02-22
申请号：US12329880
申请日：2008-12-08
申请人： Suk-Soo Pyo , Uk-Song Kang
发明人： Suk-Soo Pyo , Uk-Song Kang
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/408 , G11C2207/104 , G11C2211/4061
摘要： Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.
摘要翻译：提供了具有降低的功耗的动态随机存取存储器件以及确定动态随机存取存储器件的刷新周期的方法。该方法包括：在第一至第n自刷新周期期间选择一个或多个监视位，其中“n”是等于或大于1的自然数; 检测在第（n + 1）至第m自刷新周期期间监视比特是否具有错误，其中“m”是等于或大于n + 1的自然数; 以及根据监视位是否具有错误来调整第（m + 1）个自刷新周期。

10. 发明申请

US20090168571A1 DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF 失效
标题翻译：动态随机访问存储器件及其确定周期的方法
公开(公告)号：US20090168571A1
公开(公告)日：2009-07-02
申请号：US12329880
申请日：2008-12-08
申请人： Suk-Soo Pyo , Uk-Song Kang
发明人： Suk-Soo Pyo , Uk-Song Kang
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/408 , G11C2207/104 , G11C2211/4061
摘要： Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.
摘要翻译：提供了具有降低的功耗的动态随机存取存储器件以及确定动态随机存取存储器件的刷新周期的方法。该方法包括：在第一至第n自刷新周期期间选择一个或多个监视位，其中“n”是等于或大于1的自然数; 检测在第（n + 1）至第m自刷新周期期间监视比特是否具有错误，其中“m”是等于或大于n + 1的自然数; 以及根据监视位是否具有错误来调整第（m + 1）个自刷新周期。

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