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1. 发明申请

US20080293215A1 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
公开(公告)号：US20080293215A1
公开(公告)日：2008-11-27
申请号：US12219737
申请日：2008-07-28
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

2. 发明授权

US07807517B2 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US07807517B2
公开(公告)日：2010-10-05
申请号：US12219737
申请日：2008-07-28
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

3. 发明授权

US07419859B2 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US07419859B2
公开(公告)日：2008-09-02
申请号：US11505335
申请日：2006-08-17
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/84 , H01L29/94
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

4. 发明申请

US20070048934A1 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US20070048934A1
公开(公告)日：2007-03-01
申请号：US11505335
申请日：2006-08-17
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

5. 发明申请

US20090166714A1 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20090166714A1
公开(公告)日：2009-07-02
申请号：US12318451
申请日：2008-12-30
申请人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
发明人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
IPC分类号： H01L29/792
CPC分类号： H01L27/11568
摘要： A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.
摘要翻译：非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层，隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

6. 发明授权

US07867849B2 Method of manufacturing a non-volatile semiconductor device 有权
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US07867849B2
公开(公告)日：2011-01-11
申请号：US12222074
申请日：2008-08-01
申请人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
发明人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.
摘要翻译：示例实施例涉及制造非易失性存储器件的方法。根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底的上表面上形成至少一个栅极结构。至少一个栅极结构可以包括隧道绝缘层图案，电荷存储层图案，电介质层图案和控制栅极。根据示例实施例，制造非易失性存储器件的方法还可以包括在衬底的上表面上形成氮化硅层以覆盖至少一个栅极结构，在氮化硅层上形成绝缘中间层并且朝向基板的上表面和基板的下表面提供退火气体，以固化隧道绝缘层图案的缺陷。

7. 发明授权

US08455344B2 Method of manufacturing non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08455344B2
公开(公告)日：2013-06-04
申请号：US13238084
申请日：2011-09-21
申请人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
发明人： Suk-Kang Sung , Choong-Ho Lee , Dong-Uk Choi , Hee-Soo Kang
IPC分类号： H01L21/28
CPC分类号： H01L27/11568
摘要： A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.
摘要翻译：非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层，隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

8. 发明授权

US08158480B2 Method of forming a pattern for a semiconductor device, method of forming a charge storage pattern using the same method, non-volatile memory device and methods of manufacturing the same 有权
标题翻译：用于形成半导体器件的图案的方法，使用相同方法形成电荷存储图案的方法，非易失性存储器件及其制造方法
公开(公告)号：US08158480B2
公开(公告)日：2012-04-17
申请号：US12213305
申请日：2008-06-18
申请人： Hee-Soo Kang , Choong-Ho Lee , Suk-Kang Sung , Se-Jun Park
发明人： Hee-Soo Kang , Choong-Ho Lee , Suk-Kang Sung , Se-Jun Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11529 , H01L21/28273 , H01L27/105 , H01L27/11526 , H01L27/11531
摘要： A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate.
摘要翻译：提供一种形成半导体器件图案的方法，形成电荷存储图案的方法，包括电荷存储图案的非易失性存储器件及其制造方法。形成电荷存储图案的方法包括在衬底上形成沟槽，以及在沟槽中形成器件隔离图案。器件隔离图案从衬底的表面突出出来，形成露出衬底的开口。在开口中的基板上形成隧道氧化物层。通过导电材料的选择性沉积，在隧道氧化物层和器件隔离图案上形成初步电荷存储图案。初步电荷存储图案可以从器件隔离图案中去除。初始电荷存储图案仅保留在隧道氧化物层上，以在基板上形成电荷存储图案。

9. 发明授权

US08120091B2 Non-volatile memory devices including a floating gate and methods of manufacturing the same 有权
标题翻译：包括浮动栅极的非易失性存储器件及其制造方法
公开(公告)号：US08120091B2
公开(公告)日：2012-02-21
申请号：US12128078
申请日：2008-05-28
申请人： Suk-Kang Sung , Choong-Ho Lee , Sang-wook Lim , Dong-Uk Choi , Hee-Soo Kang , Kyu-Charn Park
发明人： Suk-Kang Sung , Choong-Ho Lee , Sang-wook Lim , Dong-Uk Choi , Hee-Soo Kang , Kyu-Charn Park
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction.
摘要翻译：非易失性存储器件包括衬底和隧道绝缘层图案，使得隧道绝缘图案的每个部分沿着第一方向延伸，并且隧道绝缘层图案的相邻部分可以在基本垂直的第二方向上分离到第一个方向。非易失性存储器件可以包括形成在隧道绝缘层图案上的栅极结构。栅极结构可以包括沿着第二方向形成在隧道绝缘层图案上的浮动栅极，在第二方向上形成在浮置栅极上的第一导电层图案，沿着第二方向形成在第一导电层图案上的电介质层图案以及在第二方向上形成在电介质层图案上的控制栅极。

10. 发明授权

US07615437B2 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07615437B2
公开(公告)日：2009-11-10
申请号：US12153071
申请日：2008-05-13
申请人： Suk-Kang Sung , Kyu-Charn Park , Choong-Ho Lee
发明人： Suk-Kang Sung , Kyu-Charn Park , Choong-Ho Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/743 , H01L21/28123 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components.
摘要翻译：一种制造非易失性存储器件的方法包括在衬底上依次沉积第一绝缘层，电荷存储层和第二绝缘层，形成通过所得结构的第一开口以露出衬底，形成第二和第三开口通过第二绝缘层形成第二绝缘层图案，在第二绝缘层图案上形成导电层，在导电层上形成光致抗蚀剂图形结构，同时形成共同的源极线，至少一个接地选择线，至少一个串选择线，以及通过蚀刻通过光致抗蚀剂图案结构在衬底上的多个栅极结构，其中公共源极线和栅极结构同时形成在基本相同的水平面上并且基本上相同的部件。

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