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    • 5. 发明授权
    • Sub-quarter micron silicon-on-insulator MOS field effect transistor with
deep silicide contact layers
    • 具有深硅化物接触层的二分之一微米绝缘体上的MOS场效应晶体管
    • US6160293A
    • 2000-12-12
    • US176914
    • 1998-10-22
    • Hideaki OnishiKiyotaka Imai
    • Hideaki OnishiKiyotaka Imai
    • H01L29/45H01L29/786H01L29/00
    • H01L29/78612H01L29/458
    • A semiconductor thin film structure includes source/drain regions and a channel region positioned between the source/drain regions. The semiconductor thin film structure extends directly on and in contact with a surface of an insulation region. At least one of the source/drain regions includes a semiconductor material region extending directly over and in contact with the surface of the insulation region and a refractory metal silicide layer extending directly on and in contact with the semiconductor material region. The refractory metal silicide layer has a first thickness which is equal to or thicker than a half of a second thickness of the channel region, thereby suppressing any substantive kink effect. The first thickness of the refractory metal silicide layer is also thinner than a third thickness of the source/drain regions, so that at least a majority part of a bottom surface of the refractory metal silicide layer has a junction interface with the semiconductor material region of the source/drain regions, thereby reducing a parasitic resistance of the source and drain regions.
    • 半导体薄膜结构包括源极/漏极区域和位于源极/漏极区域之间的沟道区域。 半导体薄膜结构直接在绝缘区域的表面上进行接触。 源极/漏极区域中的至少一个包括直接在绝缘区域的表面上和与绝缘区域的表面接触的半导体材料区域和直接在半导体材料区域上接触并且与半导体材料区域接触的难熔金属硅化物层。 难熔金属硅化物层的第一厚度等于或大于通道区域的第二厚度的一半,从而抑制任何实质的扭结效应。 难熔金属硅化物层的第一厚度也比源极/漏极区域的第三厚度薄,使得难熔金属硅化物层的底表面的至少大部分部分具有与半导体材料区域的接合界面 源极/漏极区域,从而减小源极和漏极区域的寄生电阻。
    • 10. 发明授权
    • Semiconductor integrated circuit device containing MOS protection circuit
    • 包含MOS保护电路的半导体集成电路器件
    • US5856693A
    • 1999-01-05
    • US516929
    • 1995-08-18
    • Hideaki Onishi
    • Hideaki Onishi
    • H01L27/04H01L21/822H01L21/8234H01L27/02H01L27/088H01L29/78H01L23/62
    • H01L29/7833H01L27/0266H01L2924/0002
    • A semiconductor integrated circuit device containing a protection MOSFET. This MOSFET has source and drain regions and a channel region formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The source region is made of a first lightly doped region and a first heavily doped region. The first lightly doped region is adjacent to a first end of the channel region. The drain region is made of a second lightly doped region and a second heavily doped region. The second lightly doped region is adjacent to a second end of the channel region. The second end of the channel region is positioned on an opposite side to that of the first end. A distance from the second end of the channel region to an opposing end of the second heavily doped region is longer than a distance from the first end of the channel region to an opposing end of the first heavily doped region. Even if the snapback voltage of the MOSFET fluctuates from place to place in the same MOSFET, the snapback phenomenon tends to occur within the entire drain region almost simultaneously, enabling to improve the ESD breakdown resistance of the protection MOSFET.
    • 一种包含保护MOSFET的半导体集成电路器件。 该MOSFET具有源极和漏极区域以及形成在半导体衬底中的沟道区域。 沟道区域设置在源区和漏区之间。 源极区域由第一轻掺杂区域和第一重掺杂区域制成。 第一轻掺杂区域与沟道区域的第一端相邻。 漏极区域由第二轻掺杂区域和第二重掺杂区域制成。 第二轻掺杂区域与沟道区域的第二端相邻。 通道区域的第二端位于与第一端相反的一侧。 从沟道区的第二端到第二重掺杂区的相对端的距离比从沟道区的第一端到第一重掺杂区的相对端的距离长。 即使MOSFET的快速恢复电压从同一个MOSFET的位置发生波动,几乎同时也会在整个漏极区域内发生快速反应现象,从而能够提高保护MOSFET的ESD击穿电阻。