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1. 发明授权

US06211574B1 Semiconductor package with wire protection and method therefor 有权
标题翻译：具有电线保护的半导体封装及其方法
公开(公告)号：US06211574B1
公开(公告)日：2001-04-03
申请号：US09292742
申请日：1999-04-16
申请人： Su Tao , Chun-Hung Lin , Tai-Chun Huang
发明人： Su Tao , Chun-Hung Lin , Tai-Chun Huang
IPC分类号： H01L2348
CPC分类号： H01L23/16 , H01L21/56 , H01L24/48 , H01L24/49 , H01L2224/05599 , H01L2224/4899 , H01L2224/49171 , H01L2224/85399 , H01L2224/8592 , H01L2924/00014 , H01L2924/181 , H01L2924/3862 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor package includes a semiconductor die mounted on an upper surface of a substrate. A number of wire bonds electrically connect between a number of bonding pads on the upper surface of the substrate and a number of bonding pads on an upper surface of the semiconductor die. A fixing portion surrounds the semiconductor die and covers a mediate portion of each wire bond. Encapsulating material is molded over the semiconductor die and the wire bonds to form an encapsulant. In an alternative embodiment, the fixing portion is provided on the upper surface of the substrate adjacent to a mold gate of the substrate where the wire sweeping is most likely to occur while molding. The fixing portion does not cover the semiconductor die to avoid thermal strain acting on the semiconductor die due to the different coefficients of thermal expansion between the fixing portion and the encapsulant.
摘要翻译：半导体封装包括安装在基板的上表面上的半导体管芯。多个引线键合电连接在衬底的上表面上的多个接合焊盘和半导体管芯的上表面上的多个接合焊盘之间。固定部围绕半导体管芯并覆盖每个引线接合的中间部分。封装材料被模制在半导体管芯上并且引线键合以形成密封剂。在替代实施例中，固定部分设置在与基板的模具浇口相邻的基板的上表面上，其中在模制时最可能发生金属丝扫掠。由于固定部和密封剂之间的热膨胀系数不同，固定部不覆盖半导体管芯，以避免作用在半导体管芯上的热应变。

2. 发明授权

US06369439B1 Strip of semiconductor package 有权
标题翻译：半导体封装条
公开(公告)号：US06369439B1
公开(公告)日：2002-04-09
申请号：US09366637
申请日：1999-08-04
申请人： Su Tao , Kuo-Pin Yang , Tai-Chun Huang
发明人： Su Tao , Kuo-Pin Yang , Tai-Chun Huang
IPC分类号： H01L23465
CPC分类号： H01L23/13 , H01L24/97 , H01L2224/48091 , H01L2224/4824 , H01L2924/3511 , H01L2924/00014
摘要： A strip mainly includes a plurality of guide holes, a plurality of position holes, a plurality of separation holes, a plurality of second slots and a plurality of substrate areas. Guide holes are arranged on two sides of the strip for carrying during processing, and position holes are arranged at four corners of the strip for positioning on the machine during processing. Separation holes and slots are to be contiguous to the substrate areas and separate the substrate areas from one another so that the discontinuous warpage of the substrate area affects the peripheral substrate areas. Therefore, it can reduce the chance of breaking chip in the substrate area. The two ends of the substrate are adjacent to the slots to reduce the stress of other substrates in the longitudinal direction actuating the chip during heat treatment in processing. The strip further includes a metal layer surrounding the substrate areas to increase the stiffness of the entirety of the strip.
摘要翻译：一条带主要包括多个导向孔，多个位置孔，多个分隔孔，多个第二槽和多个基板区域。引导孔布置在条的两侧，用于在加工过程中传送，并且定位孔布置在条的四个角处，用于在加工期间定位在机器上。分离孔和槽将与衬底区域相邻并且将衬底区域彼此分开，使得衬底区域的不连续翘曲影响外围衬底区域。因此，可以减少在基板区域中芯片断裂的机会。衬底的两端与槽相邻，以减少处理过程中热处理期间致动芯片的纵向方向上的其它衬底的应力。条带还包括围绕衬底区域的金属层，以增加整个条带的刚度。

3. 发明授权

US06229702B1 Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability 有权
标题翻译：球栅阵列半导体封装具有改进的散热效率，整体电性能和增强的接合能力
公开(公告)号：US06229702B1
公开(公告)日：2001-05-08
申请号：US09323904
申请日：1999-06-02
申请人： Su Tao , Chin-Long Wu , Tai-Chun Huang , Han-Hsiang Huang , Shih-Kuang Chen , Shin-Hua Chao
发明人： Su Tao , Chin-Long Wu , Tai-Chun Huang , Han-Hsiang Huang , Shih-Kuang Chen , Shin-Hua Chao
IPC分类号： H05K720
CPC分类号： H01L23/4334 , H01L23/3675 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L2224/05599 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/16151 , H01L2924/16152 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A ball grid array semiconductor package includes a substrate, a die mounted on the substrate and electrically connected to the substrate by bonding wires, a heat ring mounted on the substrate to surround the die and the bonding wires, and a heat slug mounted on the heat ring to entirely cover the die and the bonding wires thereby providing improved heat dissipation efficiency and overall electrical performance. Encapsulation material is filled into an inner space surrounded by the heat ring, heat slug and substrate to form an encapsulant for protecting the die and bonding wires. The heat ring and heat slug has at least a portion of surface area sequentially coated with a metal medium layer and an insulation layer to enhance the bonding degree between the encapsulant and the heat ring and heat slug.
摘要翻译：球栅阵列半导体封装包括基板，安装在基板上并通过接合线电连接到基板的芯片，安装在基板上以围绕晶片和接合线的热环，以及安装在热源上的散热片环以完全覆盖模具和接合线，从而提供改善的散热效率和整体电气性能。将封装材料填充到由热环，热块和衬底包围的内部空间中，以形成用于保护管芯和接合线的密封剂。热环和热块具有至少一部分表面积顺序地涂覆有金属介质层和绝缘层，以增强密封剂与热环和加热块之间的结合度。

4. 发明授权

US06692581B2 Solder paste for fabricating bump 有权
标题翻译：用于制造凸块的焊膏
公开(公告)号：US06692581B2
公开(公告)日：2004-02-17
申请号：US10248802
申请日：2003-02-20
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Ching-Fu Horng , Shih-Kuang Chen , Shyh-Ing Wu , Chun-Hung Lin , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Ching-Fu Horng , Shih-Kuang Chen , Shyh-Ing Wu , Chun-Hung Lin , Yung-Chi Lee , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： B23K35363
CPC分类号： H01L24/10 , B23K35/0244 , B23K35/025 , B23K35/262 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/0103 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H05K3/3484 , H05K2201/0266 , H05K2203/043 , H01L2924/00
摘要： A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.
摘要翻译：用于制造凸块的焊膏包括焊剂和金属合金粉末。金属合金粉末包含多个低共晶金属合金颗粒，这些金属合金颗粒的尺寸为20-60μm，金属颗粒的平均尺寸为35μm〜45μm。

5. 发明授权

US06461897B2 Multichip module having a stacked chip arrangement 有权
标题翻译：具有堆叠芯片布置的多芯片模块
公开(公告)号：US06461897B2
公开(公告)日：2002-10-08
申请号：US09854486
申请日：2001-05-15
申请人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao
发明人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/01087 , H01L2924/00014 , H01L2924/00012
摘要： A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
摘要翻译：多芯片模块包括至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。半导体芯片以堆叠方式安装到基板上，其中上芯片以下述方式附接到下芯片的有源表面，使得上芯片的任何部分不影响下芯片的每个键合焊盘的垂直视线芯片以允许其引线接合。因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

6. 发明授权

US06359340B1 Multichip module having a stacked chip arrangement 有权
标题翻译：具有堆叠芯片布置的多芯片模块
公开(公告)号：US06359340B1
公开(公告)日：2002-03-19
申请号：US09628676
申请日：2000-07-28
申请人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao , Jian Wen Chen
发明人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao , Jian Wen Chen
IPC分类号： H05K706
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2924/01087 , H01L2924/10253 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A multichip module has at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. In some embodiments, the semiconductor chips may have a plurality of bonding pads along only two mutually perpendicular side edges thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
摘要翻译：多芯片模块具有至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。在一些实施例中，半导体芯片可以具有仅沿着其两个相互垂直的侧边缘的多个接合焊盘。半导体芯片以堆叠方式安装到基板上，其中上部芯片以下述方式附接到下部芯片的有源表面，即，上部芯片的任何部分不影响下部芯片的每个焊盘的垂直视线芯片以允许其引线接合。因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

7. 发明授权

US06348729B1 Semiconductor chip package and manufacturing method thereof 有权
标题翻译：半导体芯片封装及其制造方法
公开(公告)号：US06348729B1
公开(公告)日：2002-02-19
申请号：US09390695
申请日：1999-09-07
申请人： Sai Man Li , Chun Hung Lin , Shin Hua Chao , Su Tao
发明人： Sai Man Li , Chun Hung Lin , Shin Hua Chao , Su Tao
IPC分类号： H01L2352
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01077 , H01L2924/01079 , H01L2924/181 , H01L2924/18165 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.
摘要翻译：半导体芯片封装通常包括引线框架，半导体管芯和塑料封装体。引线框架包括多个引线和窗垫。窗垫通过连接杆连接到引线框架。多个引线的内端限定中心区域。窗垫设置在中心区域中并且具有限定在其中的开口。半导体管芯设置在窗垫的开口中，并且在其活性表面上形成有多个接合焊盘。引线的内端通过多根接合线与半导体管芯上的焊盘相互连接。引线框架，半导体管芯和接合线被封装在塑料封装主体中，其中引线框架的下表面和半导体管芯的后表面通过塑料封装主体露出。

8. 发明授权

US06534852B1 Ball grid array semiconductor package with improved strength and electric performance and method for making the same 有权
标题翻译：具有改进的强度和电性能的球栅阵列半导体封装及其制造方法
公开(公告)号：US06534852B1
公开(公告)日：2003-03-18
申请号：US09547096
申请日：2000-04-11
申请人： Chun Hung Lin , I Zeng Lee , Su Tao , Kun-Ching Chen
发明人： Chun Hung Lin , I Zeng Lee , Su Tao , Kun-Ching Chen
IPC分类号： H01L2352
CPC分类号： H01L24/32 , H01L23/3128 , H01L23/4334 , H01L23/49816 , H01L24/48 , H01L2224/0401 , H01L2224/05599 , H01L2224/05647 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/73265 , H01L2224/85447 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/351 , H01L2224/45099 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
摘要： Disclosed are metal reinforced layers disposed at the upper and lower surfaces of the thin substrate to reinforce the strength of the thin substrate. With reinforced strength, the thin substrate is not susceptible to deform due to temperature fluctuation during packaging process, and thus the warpage for the semiconductor package is significantly eliminated. According to another aspect of the present invention, the metal reinforced layer at the lower surface of the thin substrate is functioned as a ground plane for the ball grid array (BGA) semiconductor package for better grounding effect. The present invention provides an optimal design for the return current path and impedance matching control. Besides, in high frequency application, the metal reinforced layer also can reduce the noise and cross talk among the signal lines of the ball grid array (BGA) semiconductor package.
摘要翻译：公开了设置在薄基板的上表面和下表面处的金属加强层，以增强薄基板的强度。由于加强强度，薄的基板由于包装过程中的温度波动而不易变形，因此显着地消除了半导体封装的翘曲。根据本发明的另一方面，薄基板的下表面处的金属增强层用作球栅阵列（BGA）半导体封装的接地平面，以获得更好的接地效果。本发明为返回电流路径和阻抗匹配控制提供了最佳设计。此外，在高频应用中，金属加强层还可以减少球栅阵列（BGA）半导体封装的信号线之间的噪声和串扰。

9. 发明授权

US06252305B1 Multichip module having a stacked chip arrangement 有权
标题翻译：具有堆叠芯片布置的多芯片模块
公开(公告)号：US06252305B1
公开(公告)日：2001-06-26
申请号：US09516025
申请日：2000-02-29
申请人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao
发明人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao
IPC分类号： H01L2348
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/01087 , H01L2924/00014 , H01L2924/00012
摘要： A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
摘要翻译：多芯片模块包括至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。半导体芯片以堆叠方式安装到基板上，其中上芯片以下述方式附接到下芯片的有源表面，使得上芯片的任何部分不影响下芯片的每个键合焊盘的垂直视线芯片以允许其引线接合。因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

10. 发明授权

US06312976B1 Method for manufacturing leadless semiconductor chip package 有权
标题翻译：无铅半导体芯片封装的制造方法
公开(公告)号：US06312976B1
公开(公告)日：2001-11-06
申请号：US09444366
申请日：1999-11-22
申请人： Chun Hung Lin , Chun-Chi Lee , Su Tao
发明人： Chun Hung Lin , Chun-Chi Lee , Su Tao
IPC分类号： H01L2144
CPC分类号： H01L21/565 , H01L23/49548 , H01L23/49833 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： A method of manufacturing a leadless semiconductor chip package comprises the steps of: attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; wire bonding the inner ends of the leads to bonding pads on the semiconductor die; sucking a film against a lower part of a molding die; closing and clamping the molding die in a manner that the semiconductor die is positioned in a cavity of the molding die and the lead frame is disposed against the film; transferring a hardenable molding compound into the cavity; hardening the molding compound; opening the molding die to take out the molded product; and punching the molded product along the notches of the leads thereby making the singulation process more convenient and correct. The lower surface of each lead of the lead frame according to the present invention is smaller than the upper surface thereof such that each lead has a tapered profile which cooperates with the film to provide better sealing effect thereby preventing the formation of flash.
摘要翻译：一种制造无引线半导体芯片封装的方法包括以下步骤：将半导体管芯附接到引线框架的管芯焊盘上，其中引线框架包括围绕管芯焊盘的周边布置的多个引线，并且每个引线具有缺口形成在被打孔的位置; 将引线的内端引线接合到半导体管芯上的接合焊盘; 将薄膜吸附在成型模具的下部; 以半导体管芯位于成型模具的空腔中的方式封闭和夹紧成型模具，并且引线框架抵靠薄膜设置; 将可硬化的模塑料转移到所述空腔中; 硬化模塑料; 打开成型模具取出成型品; 沿着导线的切口冲压模制产品，从而使切割过程更方便正确。根据本发明的引线框架的每个引线的下表面小于其上表面，使得每个引线具有与膜配合的锥形轮廓，以提供更好的密封效果，从而防止闪光的形成。

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