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1. 发明申请

US20090040842A1 Enhanced write abort mechanism for non-volatile memory 审中-公开
公开(公告)号：US20090040842A1
公开(公告)日：2009-02-12
申请号：US11890708
申请日：2007-08-06
申请人： Steven T. Sprouse , Dhaval Parikh , Arjun Kapoor
发明人： Steven T. Sprouse , Dhaval Parikh , Arjun Kapoor
IPC分类号： G11C7/00
CPC分类号： G11C16/225
摘要： In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal.

2. 发明申请

US20090040843A1 Enhanced write abort mechanism for non-volatile memory 有权
公开(公告)号：US20090040843A1
公开(公告)日：2009-02-12
申请号：US11890734
申请日：2007-08-06
申请人： Steven T. Sprouse , Dhaval Parikh , Arjun Kapoor
发明人： Steven T. Sprouse , Dhaval Parikh , Arjun Kapoor
IPC分类号： G11C7/00
CPC分类号： G11C16/225
摘要： In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal.

3. 发明授权

US07599241B2 Enhanced write abort mechanism for non-volatile memory 有权
标题翻译：用于非易失性存储器的增强写入中止机制
公开(公告)号：US07599241B2
公开(公告)日：2009-10-06
申请号：US11890734
申请日：2007-08-06
申请人： Steven T. Sprouse , Dhaval Parikh , Arjun Kapoor
发明人： Steven T. Sprouse , Dhaval Parikh , Arjun Kapoor
IPC分类号： G11C5/14
CPC分类号： G11C16/225
摘要： In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal.
摘要翻译：在具有由控制器控制的控制器和非易失性存储器阵列的非易失性存储器（NVM）器件中，电压监控器电路监视为NVM器件供电的电压源的输出。电压监控器电路可以是NVM器件的一部分或耦合到其上。电压监控器电路被配置为响应于检测到NVM器件供电的电压输出下降到预定值以下来断言“低电压”信号。控制器被配置为在“低电压”信号被断言时将数据写入存储器阵列，并且在“低电压”信号被断言时暂停写入数据。响应于“低电压”信号的声明，控制器完成写入周期/编程操作，如果挂起，并且在断言“低电压”信号期间防止任何额外的写周期/编程操作。

4. 发明授权

US07697325B2 Non-volatile memory cell endurance using data encoding 有权
标题翻译：使用数据编码的非易失性存储单元耐久性
公开(公告)号：US07697325B2
公开(公告)日：2010-04-13
申请号：US11903764
申请日：2007-09-24
申请人： Steven T. Sprouse , Dhaval Parikh , Sukhminder S. Lobana , Shai Traister
发明人： Steven T. Sprouse , Dhaval Parikh , Sukhminder S. Lobana , Shai Traister
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/1006
摘要： A method and apparatus for storing an n-bit (for n>=2) data block in an array of non-volatile memory cells utilizes a predetermined n+k-bit (for k>=1) encoding selected to reduce the number of programmed cells required to store the n-bit data block.
摘要翻译：用于在非易失性存储器单元阵列中存储n位（对于n> = 2）数据块的方法和装置利用所选择的编码的预定n + k位（对于k> = 1）来减少编号存储n位数据块所需的编程单元。

5. 发明申请

US20100161927A1 Method for Using a CAPTCHA Challenge to Protect a Removable Mobile Flash Memory Storage Device 有权
标题翻译：使用CAPTCHA挑战来保护可拆卸移动闪存存储设备的方法
公开(公告)号：US20100161927A1
公开(公告)日：2010-06-24
申请号：US12338696
申请日：2008-12-18
申请人： Steven T. Sprouse , Carlos J. Gonzalez , Ron Barzilai , Dhaval Parikh
发明人： Steven T. Sprouse , Carlos J. Gonzalez , Ron Barzilai , Dhaval Parikh
IPC分类号： G06F12/14
CPC分类号： G06F21/79 , G06F21/36 , G06F2221/2133
摘要： The embodiments described herein generally use a challenge to protect a removable mobile flash memory storage device, where the challenge may be in the form of a “Completely Automated Public Turing Test to Tell Computers and Humans Apart” (“CAPTCHA”). In one embodiment, a method is provided in which a removable mobile flash memory storage device receives a command from a host device, generates a CAPTCHA challenge, provides the CAPTCHA challenge to the host device, receives a response to the CAPTCHA challenge from the host device, determines if the response satisfies the CAPTCHA challenge, and performs the command only if the response satisfies the CAPTCHA challenge. In another embodiment, a removable mobile flash memory storage device is provided for performing these acts.
摘要翻译：本文描述的实施例通常使用保护可移动的移动闪存存储设备的挑战，其中挑战可以是“完全自动公共图灵测试以告知计算机和人类之外”（“CAPTCHA”）的形式。在一个实施例中，提供了一种方法，其中可移除的移动闪存存储设备从主机设备接收命令，生成CAPTCHA挑战，向主机设备提供CAPTCHA挑战，从主机设备接收对CAPTCHA挑战的响应，确定响应是否满足CAPTCHA挑战，并且仅当响应满足CAPTCHA挑战时才执行命令。在另一个实施例中，提供了用于执行这些动作的可拆卸移动闪存存储设备。

6. 发明授权

US07416419B2 Methods for ESD protection 有权
标题翻译： ESD保护方法
公开(公告)号：US07416419B2
公开(公告)日：2008-08-26
申请号：US11465049
申请日：2006-08-16
申请人： Patricio Collantes, Jr. , Robert C. Miller , Steven T. Sprouse , Dhaval Parikh
发明人： Patricio Collantes, Jr. , Robert C. Miller , Steven T. Sprouse , Dhaval Parikh
IPC分类号： H01R12/00
CPC分类号： H05K9/0067 , H01R13/6582
摘要： A Universal Serial Bus flash memory unit having an electrically conductive housing includes a spring that provides an electrically conductive, low-resistance pathway between the housing and the metal shell of the Universal Serial Bus connector so that electrostatic charge can directly discharge from the housing to the metal shell instead of discharging through electronic components within the housing.
摘要翻译：具有导电壳体的通用串行总线闪速存储器单元包括弹簧，其在壳体和通用串行总线连接器的金属壳之间提供导电的低电阻通路，使得静电荷可以直接从壳体排出到金属外壳，而不是通过外壳内的电子元件放电。

7. 发明授权

US08688940B2 Method for using a CAPTCHA challenge to protect a removable mobile flash memory storage device 有权
标题翻译：使用CAPTCHA挑战来保护可移动的移动闪存存储设备的方法
公开(公告)号：US08688940B2
公开(公告)日：2014-04-01
申请号：US12338696
申请日：2008-12-18
申请人： Steven T. Sprouse , Carlos J. Gonzalez , Ron Barzilai , Dhaval Parikh
发明人： Steven T. Sprouse , Carlos J. Gonzalez , Ron Barzilai , Dhaval Parikh
IPC分类号： G06F12/00
CPC分类号： G06F21/79 , G06F21/36 , G06F2221/2133
摘要： The embodiments described herein generally use a challenge to protect a removable mobile flash memory storage device, where the challenge may be in the form of a “Completely Automated Public Turing Test to Tell Computers and Humans Apart” (“CAPTCHA”). In one embodiment, a method is provided in which a removable mobile flash memory storage device receives a command from a host device, generates a CAPTCHA challenge, provides the CAPTCHA challenge to the host device, receives a response to the CAPTCHA challenge from the host device, determines if the response satisfies the CAPTCHA challenge, and performs the command only if the response satisfies the CAPTCHA challenge. In another embodiment, a removable mobile flash memory storage device is provided for performing these acts.
摘要翻译：本文描述的实施例通常使用保护可移动的移动闪存存储设备的挑战，其中挑战可以是“完全自动公共图灵测试以告知计算机和人类之外”（“CAPTCHA”）的形式。在一个实施例中，提供了一种方法，其中可移除的移动闪存存储设备从主机设备接收命令，生成CAPTCHA挑战，向主机设备提供CAPTCHA挑战，从主机设备接收对CAPTCHA挑战的响应，确定响应是否满足CAPTCHA挑战，并且仅当响应满足CAPTCHA挑战时才执行命令。在另一个实施例中，提供了用于执行这些动作的可拆卸移动闪存存储设备。

8. 发明申请

US20090085221A1 Multi-host interface controller with USB PHY/analog functions integrated in a single package 有权
标题翻译：具有USB PHY /模拟功能的多主机接口控制器集成在单个封装中
公开(公告)号：US20090085221A1
公开(公告)日：2009-04-02
申请号：US11906582
申请日：2007-10-02
申请人： Steven T. Sprouse , Dhaval Parikh , Michael McCarthy
发明人： Steven T. Sprouse , Dhaval Parikh , Michael McCarthy
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L25/18 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2225/0651 , H01L2924/00014
摘要： In a first embodiment, an apparatus and a method of fabrication thereof includes a substrate, a controller formed on a first integrated circuit (IC) die and disposed on the substrate, a second IC die embodying circuitry configured to enable communication between the controller and an external device, first I/O pads disposed on the first IC die, second I/O pads disposed on the second IC die, wire bonding interconnections coupling at least one of the first I/O pads with at least one of the second I/O pads, and a memory array formed on a third IC die and configured to enable communication with the controller. In a second embodiment the memory array is alternatively integrated into the first IC die.
摘要翻译：在第一实施例中，一种装置及其制造方法包括：衬底，形成在第一集成电路（IC）管芯上并设置在衬底上的控制器;控制器，被配置为使能控制器与控制器之间的通信; 外部设备，设置在第一IC裸片上的第一I / O焊盘，设置在第二IC裸片上的第二I / O焊盘，将至少一个第一I / O焊盘与至少一个第二I / O焊盘和形成在第三IC裸片上并被配置为实现与控制器的通信的存储器阵列。在第二实施例中，存储器阵列可选地集成到第一IC芯片中。

9. 发明申请

US20090080249A1 Non-volatile memory cell endurance using data encoding 有权
标题翻译：使用数据编码的非易失性存储单元耐久性
公开(公告)号：US20090080249A1
公开(公告)日：2009-03-26
申请号：US11903764
申请日：2007-09-24
申请人： Steven T. Sprouse , Dhaval Parikh , Sukhminder S. Lobana , Shai Traister
发明人： Steven T. Sprouse , Dhaval Parikh , Sukhminder S. Lobana , Shai Traister
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C7/1006
摘要： A method and apparatus for storing an n-bit (for n>=2) data block in an array of non-volatile memory cells utilizes a predetermined n+k-bit (for k>=1) encoding selected to reduce the number of programmed cells required to store the n-bit data block.
摘要翻译：用于在非易失性存储器单元的阵列中存储n位（对于n> = 2）数据块的方法和装置利用所选择的编码的预定n + k位（对于k> = 1）来减少编号存储n位数据块所需的编程单元。

10. 发明授权

US07898091B2 Multi-host interface controller with USB PHY/analog functions integrated in a single package 有权
标题翻译：具有USB PHY /模拟功能的多主机接口控制器集成在单个封装中
公开(公告)号：US07898091B2
公开(公告)日：2011-03-01
申请号：US11906582
申请日：2007-10-02
申请人： Steven T. Sprouse , Dhaval Parikh , Michael McCarthy
发明人： Steven T. Sprouse , Dhaval Parikh , Michael McCarthy
IPC分类号： H01L23/48
CPC分类号： H01L25/18 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2225/0651 , H01L2924/00014
摘要： In a first embodiment, an apparatus and a method of fabrication thereof includes a substrate, a controller formed on a first integrated circuit (IC) die and disposed on the substrate, a second IC die embodying circuitry configured to enable communication between the controller and an external device, first I/O pads disposed on the first IC die, second I/O pads disposed on the second IC die, wire bonding interconnections coupling at least one of the first I/O pads with at least one of the second I/O pads, and a memory array formed on a third IC die and configured to enable communication with the controller. In a second embodiment the memory array is alternatively integrated into the first IC die.
摘要翻译：在第一实施例中，一种装置及其制造方法包括：衬底，形成在第一集成电路（IC）管芯上并设置在衬底上的控制器;控制器，被配置为使能控制器与控制器之间的通信，外部设备，设置在第一IC裸片上的第一I / O焊盘，设置在第二IC裸片上的第二I / O焊盘，将至少一个第一I / O焊盘与至少一个第二I / O焊盘和形成在第三IC裸片上并被配置为实现与控制器的通信的存储器阵列。在第二实施例中，存储器阵列可选地集成到第一IC芯片中。

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