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1. 发明授权

US06193422B1 Implementation of idle mode in a suspend/resume microprocessor system 失效
标题翻译：在暂停/恢复微处理器系统中实现空闲模式
公开(公告)号：US06193422B1
公开(公告)日：2001-02-27
申请号：US08264182
申请日：1994-06-22
申请人： Steven L. Belt , Robert J. Grabon , Chandrakant H. Pandya , Jiming Sun , Neysa K. Terry-Gray , Min E. Lee , Norman M. Hack
发明人： Steven L. Belt , Robert J. Grabon , Chandrakant H. Pandya , Jiming Sun , Neysa K. Terry-Gray , Min E. Lee , Norman M. Hack
IPC分类号： G06F1310
CPC分类号： G06F1/24 , G06F1/3203
摘要： A portable computer system includes an input device such as a keyboard, a display, and a processor which is operable in a normal operational mode and in a reduced power mode, the processor carrying out program execution in each of the normal operational mode and reduced power mode. A timing arrangement switches the processor from its normal operational mode to its reduced power mode in response to the absence of any of a plurality of predetermined events during a predetermined time interval, the predetermined events including actuation of keys on the keyboard and transmission of information to the video display.
摘要翻译：便携式计算机系统包括诸如键盘，显示器和处理器的输入设备，其可以在正常操作模式和降低功率模式下操作，处理器在每个正常操作模式和降低的功率下执行程序执行模式。响应于在预定时间间隔期间不存在多个预定事件中的任何一个，定时装置将处理器从其正常操作模式切换到其降低功率模式，预定事件包括键盘上的键的激活和信息的传送视频显示。

2. 发明授权

US06295573B1 Point-to-point interrupt messaging within a multiprocessing computer system 有权
标题翻译：多处理计算机系统内的点对点中断消息传递
公开(公告)号：US06295573B1
公开(公告)日：2001-09-25
申请号：US09251266
申请日：1999-02-16
申请人： Joseph A. Bailey , Norman M. Hack
发明人： Joseph A. Bailey , Norman M. Hack
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： An interrupt messaging scheme to manage interrupts within a multiprocessing computer system without a dedicated interrupt bus. An interconnect structure using a plurality of high-speed dual-unidirectional links to interconnect processing nodes, I/O devices or I/O bridges in the multiprocessing system is implemented. Interrupt messages are transferred as discrete binary packets over point-to-point unidirectional links. A suitable routing algorithm may be employed to route various interrupt packets within the system. Simultaneous transmission of interrupt messages from two or more processing nodes and I/O bridges may be possible without any need for bus arbitration. Interrupt packets carry routing and destination information to identify source and destination processing nodes for interrupt delivery. A lowest priority interrupt packet from an I/O bridge is converted into a coherent form by the host processing node coupled to the I/O bridge. The host node then broadcasts the coherent interrupt packet to all other processing nodes in the system regardless of whether a processing node is identified as a target in the interrupt message packet from the I/O bridge. The host node also receives responses from recipient nodes and coordinates lowest priority arbitration. In case of a fixed, an ExtINT or a non-vectored interrupt message from the I/O bridge, the host node simply forwards the interrupt packets to all other nodes in the system without performing the conversion. Inter-processor interrupts may also be delivered in a similar manner. Interrupt response is decoupled from corresponding interrupt message and the interrupt messaging protocol may be implemented independently of the physical properties of a system bus carrying interrupt packets.
摘要翻译：一种用于管理多处理计算机系统中没有专用中断总线的中断消息传递方案。实现了使用多个高速双向链路来互连多处理系统中的处理节点，I / O设备或I / O桥的互连结构。中断消息作为离散二进制数据包通过点对点单向链路传输。可以采用合适的路由算法来路由系统内的各种中断分组。从两个或多个处理节点和I / O桥同时传输中断消息可能是无需总线仲裁的。中断数据包携带路由和目标信息，以识别源和目的地处理节点进行中断传递。来自I / O桥的最低优先级的中断分组由耦合到I / O桥的主机处理节点转换成相干形式。主机节点然后将相干中断分组广播到系统中的所有其他处理节点，而不管处理节点是否被识别为来自I / O桥的中断消息分组中的目标。主机节点还从接收节点接收响应，并协调最低优先权仲裁。在固定的情况下，来自I / O桥的Extron或非向量中断消息，主机节点只需将中断包转发到系统中的所有其他节点，而不执行转换。处理器间中断也可以以类似的方式传送。中断响应与相应的中断消息分离，并且中断消息传递协议可以独立于承载中断分组的系统总线的物理属性来实现。

3. 发明授权

US06205508B1 Method for distributing interrupts in a multi-processor system 有权
标题翻译：在多处理器系统中分配中断的方法
公开(公告)号：US06205508B1
公开(公告)日：2001-03-20
申请号：US09251265
申请日：1999-02-16
申请人： Joseph A. Bailey , Norman M. Hack
发明人： Joseph A. Bailey , Norman M. Hack
IPC分类号： G06F1324
CPC分类号： G06F13/26
摘要： An interrupt messaging scheme for a multiprocessing computer system where a dedicated bus to carry interrupt messages within the multiprocessing system is eliminated. Instead, an interconnect structure using a plurality of high-speed dual-unidirectional links to interconnect processing nodes, I/O devices or I/O bridges in the system is implemented. Interrupt messages are transferred as discrete binary packets over point-to-point unidirectional links. Various interrupt requests are transferred through a predetermined set of discrete interrupt message packets. Interrupt message initiators—an I/O interrupt controller or a local interrupt controller (in case of an inter-processor interrupt)—may be configured to generate appropriate interrupt message packets upon receiving an interrupt request. A suitable routing algorithm may be employed to route various interrupt messages within the system. Simultaneous transmission of interrupt messages from two or more interrupt controllers may be possible without any need for bus arbitration. Interrupt response is decoupled from corresponding interrupt message and the interrupt messaging protocol may be implemented independently of the physical properties of a system bus carrying interrupt packets. System flexibility in managing interrupts is thus improved.
摘要翻译：用于多处理计算机系统的中断消息传递方案，其中消除了在多处理系统内携带中断消息的专用总线。相反，实现了使用多个高速双向链路来互连系统中的处理节点，I / O设备或I / O桥的互连结构。中断消息作为离散二进制数据包通过点对点单向链路传输。各种中断请求通过预定的一组离散中断消息包传送。中断信息发起者 - I / O中断控制器或本地中断控制器（在处理器间中断的情况下）可以被配置为在接收到中断请求时产生适当的中断消息包。可以采用合适的路由算法来路由系统内的各种中断消息。可以在不需要总线仲裁的情况下同时传输来自两个或多个中断控制器的中断消息。中断响应与相应的中断消息分离，并且中断消息传递协议可以独立于承载中断分组的系统总线的物理属性来实现。因此改善了管理中断的系统灵活性。

4. 发明申请

US20110283124A1 METHOD AND APPARATUS FOR CACHE CONTROL 有权
标题翻译：缓存控制的方法和设备
公开(公告)号：US20110283124A1
公开(公告)日：2011-11-17
申请号：US12777657
申请日：2010-05-11
申请人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
发明人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
摘要翻译：公开了一种用于动态控制高速缓存大小的方法和装置。在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

5. 发明授权

US06832310B1 Manipulating work queue elements via a hardware adapter and software driver 有权
标题翻译：通过硬件适配器和软件驱动程序操作工作队列元素
公开(公告)号：US06832310B1
公开(公告)日：2004-12-14
申请号：US09758113
申请日：2001-01-04
申请人： Joseph A. Bailey , Norman M. Hack , Clark L. Buxton
发明人： Joseph A. Bailey , Norman M. Hack , Clark L. Buxton
IPC分类号： G06F900
CPC分类号： G06F13/387 , G06F9/4843
摘要： A method and apparatus for manipulating work queue elements via a hardware adapter and a software driver. The software driver is configured to cause a plurality of work queue elements to be stored in a queue pair including a plurality of storage locations. Each of the plurality of storage locations includes an indicator indicating whether a corresponding work queue element has been completed. The hardware adapter is configured to select one of the plurality of storage locations and to service a corresponding one of the plurality of work queue elements, and in response to completion of a task associated with the corresponding work queue element, to cause the indicator to indicate that the corresponding work queue element has been completed. Additionally, the software driver is configured to cause a new work queue element to be stored in the selected storage location in response to detecting that the indicator indicates that the corresponding work queue element has been completed.
摘要翻译：一种用于通过硬件适配器和软件驱动程序操纵工作队列元素的方法和装置。软件驱动器被配置为使得多个工作队列元素被存储在包括多个存储位置的队列对中。多个存储位置中的每一个包括指示对应的工作队列元素是否已经完成的指示符。硬件适配器被配置为选择多个存储位置中的一个并且服务多个工作队列元素中的对应的一个工作队列元素，并且响应于与对应的工作队列元素相关联的任务的完成，使得指示符指示相应的工作队列元素已经完成。此外，软件驱动器被配置为响应于检测到指示符指示相应的工作队列元素已经完成而使新的工作队列元素存储在所选择的存储位置中。

6. 发明授权

US5321827A Computer system with modular upgrade capability 失效
标题翻译：具有模块化升级功能的计算机系统
公开(公告)号：US5321827A
公开(公告)日：1994-06-14
申请号：US534888
申请日：1990-06-08
申请人： Gene Y. Lu , David L. Kelly , Norman M. Hack , Scott R. Rushford
发明人： Gene Y. Lu , David L. Kelly , Norman M. Hack , Scott R. Rushford
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4063 , Y10T70/5009
摘要： A system and method for upgrading a computer is disclosed. Certain essential chips present in the original computer system are functionally, but not necessarily physically, removed from the computer system. Functions which would otherwise be performed by the original chips are instead performed by higher-performance chips on a plug-in module which is plugged into the computer system. The functional removal of the certain chips from the original computer system is achieved through simple insertion of the plug-in module. No replacement or substitution of original chips or boards is necessary. Furthermore, upgraded computer systems may be further upgraded by replacement of a first plug-in module with a second plug-in module with different performance characteristics.
摘要翻译：公开了一种用于升级计算机的系统和方法。存在于原始计算机系统中的某些基本芯片在功能上但不一定在物理上从计算机系统中移除。否则将由原始芯片执行的功能由插入计算机系统的插件模块上的更高性能芯片执行。从原始计算机系统中去除特定芯片的功能是通过简单插入插件模块实现的。不需要更换或替换原始芯片或板卡。此外，可以通过用具有不同性能特征的第二插件模块替换第一插件模块来进一步升级升级的计算机系统。

7. 发明授权

US5297272A Apparatus for automatically disabling and isolating a computer's original processor upon installation of a processor upgrade card 失效
标题翻译：用于在安装处理器升级卡时自动禁用和隔离计算机的原始处理器的装置
公开(公告)号：US5297272A
公开(公告)日：1994-03-22
申请号：US388445
申请日：1989-08-02
申请人： Gene Y. Lu , David L. Kelly , Norman M. Hack , Scott R. Rushford
发明人： Gene Y. Lu , David L. Kelly , Norman M. Hack , Scott R. Rushford
IPC分类号： G06F13/40 , G06F15/76
CPC分类号： G06F13/4063
摘要： A system and method for upgrading a computer is disclosed. Certain essential chips present in the original computer system are functionally, but not physically, removed from the computer system. The functions which would otherwise be performed by the original chips are instead performed by higher-performance chips on a plug-in module which is plugged into the computer system. The functional removal of the certain chips from the original computer system is achieved through simple insertion of the plug-in module. No replacement or substitution of original chips or boards is necessary.
摘要翻译：公开了一种用于升级计算机的系统和方法。存在于原始计算机系统中的某些基本芯片在功能上而不是物理地从计算机系统中移除。否则将由原始芯片执行的功能由插入计算机系统的插件模块上的高性能芯片执行。从原始计算机系统中去除特定芯片的功能是通过简单插入插件模块实现的。不需要更换或替换原始芯片或板卡。

8. 发明授权

US08412971B2 Method and apparatus for cache control 有权
标题翻译：用于缓存控制的方法和装置
公开(公告)号：US08412971B2
公开(公告)日：2013-04-02
申请号：US12777657
申请日：2010-05-11
申请人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
发明人： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
IPC分类号： G06F1/26
CPC分类号： G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
摘要翻译：公开了一种用于动态控制高速缓存大小的方法和装置。在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

9. 发明授权

US07266614B1 Embedded channel adapter having link layer configured for concurrent retrieval of payload data during packet transmission 有权
标题翻译：具有链路层的嵌入式信道适配器被配置用于在分组传输期间并行检索有效载荷数据
公开(公告)号：US07266614B1
公开(公告)日：2007-09-04
申请号：US10259409
申请日：2002-09-30
申请人： Joseph D. Winkles , Joseph A. Bailey , Norman M. Hack
发明人： Joseph D. Winkles , Joseph A. Bailey , Norman M. Hack
IPC分类号： G06F15/16 , H04J3/12
CPC分类号： G06F13/385
摘要： An host channel adapter embedded within a processor device includes a transport layer module, a transport layer buffer, a link layer module, and a link layer buffer configured for storing at least two packets to be transmitted by the embedded host channel adapter. The transport layer module is configured for generating, for each packet to be transmitted, a transport layer header, and storing in the transport layer buffer the transport layer header and a corresponding identifier that specifies a stored location of a payload for the transport layer header. The link layer module includes payload fetch logic configured for fetching the payload based on the corresponding identifier, enabling the link layer module to construct one of the two packets to be transmitted concurrently during transmission of the second of the two packets.
摘要翻译：嵌入在处理器设备内的主机通道适配器包括传输层模块，传输层缓冲器，链路层模块和配置用于存储要由嵌入式主机信道适配器传输的至少两个分组的链路层缓冲器。传输层模块被配置为针对要发送的每个分组生成传输层报头，并且在传输层缓冲器中存储传输层报头和指定传输层报头的有效载荷的存储位置的对应标识符。链路层模块包括被配置为基于对应的标识符来提取有效负载的有效载荷提取逻辑，使得链路层模块能够构建在两个分组中的第二个分组的传输期间同时发送的两个分组中的一个分组。

10. 发明授权

US07076569B1 Embedded channel adapter having transport layer configured for prioritizing selection of work descriptors based on respective virtual lane priorities 有权
标题翻译：嵌入式通道适配器具有配置用于基于相应的虚拟通道优先级来优先选择工作描述符的传输层
公开(公告)号：US07076569B1
公开(公告)日：2006-07-11
申请号：US10273183
申请日：2002-10-18
申请人： Joseph A. Bailey , Joseph D. Winkles , Norman M. Hack
发明人： Joseph A. Bailey , Joseph D. Winkles , Norman M. Hack
IPC分类号： G06F15/16
CPC分类号： H04L69/12 , H04L69/324 , H04L69/326
摘要： An embedded host channel adapter includes a transport layer module, a transport layer buffer, and a link layer module. The transport layer buffer is configured for storing transmit packet entries for virtual lanes serviced by the embedded host channel adapter. The link layer module is configured for supplying virtual lane priority information and virtual lane flow control information, for each virtual lane, to the transport layer module. The link layer module also configured for constructing transmit packets to be transmitted based on retrieval thereof from the transport layer buffer. The transport layer module is configured for selecting one of the virtual lanes for servicing based on the supplied virtual lane priority information and virtual lane flow control information for each of the virtual lanes, enabling the transport layer module to prioritize received work notifications, for generation of respective transmit packet entries.
摘要翻译：嵌入式主机通道适配器包括传输层模块，传输层缓冲器和链路层模块。传输层缓冲器被配置为存储由嵌入式主机信道适配器服务的虚拟通道的发送分组条目。链路层模块被配置为向每个虚拟通道提供虚拟通道优先级信息和虚拟通道流控制信息到传输层模块。链路层模块还被配置为基于从传输层缓冲器的检索来构造要发送的发送分组。传输层模块被配置为基于所提供的虚拟通道优先级信息和用于每个虚拟通道的虚拟通道流控制信息来选择一条虚拟通道进行服务，使得传输层模块能够优先处理接收到的工作通知，以产生各自的发送分组条目。

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