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1. 发明授权

US07266614B1 Embedded channel adapter having link layer configured for concurrent retrieval of payload data during packet transmission 有权
标题翻译：具有链路层的嵌入式信道适配器被配置用于在分组传输期间并行检索有效载荷数据
公开(公告)号：US07266614B1
公开(公告)日：2007-09-04
申请号：US10259409
申请日：2002-09-30
申请人： Joseph D. Winkles , Joseph A. Bailey , Norman M. Hack
发明人： Joseph D. Winkles , Joseph A. Bailey , Norman M. Hack
IPC分类号： G06F15/16 , H04J3/12
CPC分类号： G06F13/385
摘要： An host channel adapter embedded within a processor device includes a transport layer module, a transport layer buffer, a link layer module, and a link layer buffer configured for storing at least two packets to be transmitted by the embedded host channel adapter. The transport layer module is configured for generating, for each packet to be transmitted, a transport layer header, and storing in the transport layer buffer the transport layer header and a corresponding identifier that specifies a stored location of a payload for the transport layer header. The link layer module includes payload fetch logic configured for fetching the payload based on the corresponding identifier, enabling the link layer module to construct one of the two packets to be transmitted concurrently during transmission of the second of the two packets.
摘要翻译：嵌入在处理器设备内的主机通道适配器包括传输层模块，传输层缓冲器，链路层模块和配置用于存储要由嵌入式主机信道适配器传输的至少两个分组的链路层缓冲器。传输层模块被配置为针对要发送的每个分组生成传输层报头，并且在传输层缓冲器中存储传输层报头和指定传输层报头的有效载荷的存储位置的对应标识符。链路层模块包括被配置为基于对应的标识符来提取有效负载的有效载荷提取逻辑，使得链路层模块能够构建在两个分组中的第二个分组的传输期间同时发送的两个分组中的一个分组。

2. 发明授权

US07076569B1 Embedded channel adapter having transport layer configured for prioritizing selection of work descriptors based on respective virtual lane priorities 有权
标题翻译：嵌入式通道适配器具有配置用于基于相应的虚拟通道优先级来优先选择工作描述符的传输层
公开(公告)号：US07076569B1
公开(公告)日：2006-07-11
申请号：US10273183
申请日：2002-10-18
申请人： Joseph A. Bailey , Joseph D. Winkles , Norman M. Hack
发明人： Joseph A. Bailey , Joseph D. Winkles , Norman M. Hack
IPC分类号： G06F15/16
CPC分类号： H04L69/12 , H04L69/324 , H04L69/326
摘要： An embedded host channel adapter includes a transport layer module, a transport layer buffer, and a link layer module. The transport layer buffer is configured for storing transmit packet entries for virtual lanes serviced by the embedded host channel adapter. The link layer module is configured for supplying virtual lane priority information and virtual lane flow control information, for each virtual lane, to the transport layer module. The link layer module also configured for constructing transmit packets to be transmitted based on retrieval thereof from the transport layer buffer. The transport layer module is configured for selecting one of the virtual lanes for servicing based on the supplied virtual lane priority information and virtual lane flow control information for each of the virtual lanes, enabling the transport layer module to prioritize received work notifications, for generation of respective transmit packet entries.
摘要翻译：嵌入式主机通道适配器包括传输层模块，传输层缓冲器和链路层模块。传输层缓冲器被配置为存储由嵌入式主机信道适配器服务的虚拟通道的发送分组条目。链路层模块被配置为向每个虚拟通道提供虚拟通道优先级信息和虚拟通道流控制信息到传输层模块。链路层模块还被配置为基于从传输层缓冲器的检索来构造要发送的发送分组。传输层模块被配置为基于所提供的虚拟通道优先级信息和用于每个虚拟通道的虚拟通道流控制信息来选择一条虚拟通道进行服务，使得传输层模块能够优先处理接收到的工作通知，以产生各自的发送分组条目。

3. 发明授权

US06832310B1 Manipulating work queue elements via a hardware adapter and software driver 有权
标题翻译：通过硬件适配器和软件驱动程序操作工作队列元素
公开(公告)号：US06832310B1
公开(公告)日：2004-12-14
申请号：US09758113
申请日：2001-01-04
申请人： Joseph A. Bailey , Norman M. Hack , Clark L. Buxton
发明人： Joseph A. Bailey , Norman M. Hack , Clark L. Buxton
IPC分类号： G06F900
CPC分类号： G06F13/387 , G06F9/4843
摘要： A method and apparatus for manipulating work queue elements via a hardware adapter and a software driver. The software driver is configured to cause a plurality of work queue elements to be stored in a queue pair including a plurality of storage locations. Each of the plurality of storage locations includes an indicator indicating whether a corresponding work queue element has been completed. The hardware adapter is configured to select one of the plurality of storage locations and to service a corresponding one of the plurality of work queue elements, and in response to completion of a task associated with the corresponding work queue element, to cause the indicator to indicate that the corresponding work queue element has been completed. Additionally, the software driver is configured to cause a new work queue element to be stored in the selected storage location in response to detecting that the indicator indicates that the corresponding work queue element has been completed.
摘要翻译：一种用于通过硬件适配器和软件驱动程序操纵工作队列元素的方法和装置。软件驱动器被配置为使得多个工作队列元素被存储在包括多个存储位置的队列对中。多个存储位置中的每一个包括指示对应的工作队列元素是否已经完成的指示符。硬件适配器被配置为选择多个存储位置中的一个并且服务多个工作队列元素中的对应的一个工作队列元素，并且响应于与对应的工作队列元素相关联的任务的完成，使得指示符指示相应的工作队列元素已经完成。此外，软件驱动器被配置为响应于检测到指示符指示相应的工作队列元素已经完成而使新的工作队列元素存储在所选择的存储位置中。

4. 发明授权

US06295573B1 Point-to-point interrupt messaging within a multiprocessing computer system 有权
标题翻译：多处理计算机系统内的点对点中断消息传递
公开(公告)号：US06295573B1
公开(公告)日：2001-09-25
申请号：US09251266
申请日：1999-02-16
申请人： Joseph A. Bailey , Norman M. Hack
发明人： Joseph A. Bailey , Norman M. Hack
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： An interrupt messaging scheme to manage interrupts within a multiprocessing computer system without a dedicated interrupt bus. An interconnect structure using a plurality of high-speed dual-unidirectional links to interconnect processing nodes, I/O devices or I/O bridges in the multiprocessing system is implemented. Interrupt messages are transferred as discrete binary packets over point-to-point unidirectional links. A suitable routing algorithm may be employed to route various interrupt packets within the system. Simultaneous transmission of interrupt messages from two or more processing nodes and I/O bridges may be possible without any need for bus arbitration. Interrupt packets carry routing and destination information to identify source and destination processing nodes for interrupt delivery. A lowest priority interrupt packet from an I/O bridge is converted into a coherent form by the host processing node coupled to the I/O bridge. The host node then broadcasts the coherent interrupt packet to all other processing nodes in the system regardless of whether a processing node is identified as a target in the interrupt message packet from the I/O bridge. The host node also receives responses from recipient nodes and coordinates lowest priority arbitration. In case of a fixed, an ExtINT or a non-vectored interrupt message from the I/O bridge, the host node simply forwards the interrupt packets to all other nodes in the system without performing the conversion. Inter-processor interrupts may also be delivered in a similar manner. Interrupt response is decoupled from corresponding interrupt message and the interrupt messaging protocol may be implemented independently of the physical properties of a system bus carrying interrupt packets.
摘要翻译：一种用于管理多处理计算机系统中没有专用中断总线的中断消息传递方案。实现了使用多个高速双向链路来互连多处理系统中的处理节点，I / O设备或I / O桥的互连结构。中断消息作为离散二进制数据包通过点对点单向链路传输。可以采用合适的路由算法来路由系统内的各种中断分组。从两个或多个处理节点和I / O桥同时传输中断消息可能是无需总线仲裁的。中断数据包携带路由和目标信息，以识别源和目的地处理节点进行中断传递。来自I / O桥的最低优先级的中断分组由耦合到I / O桥的主机处理节点转换成相干形式。主机节点然后将相干中断分组广播到系统中的所有其他处理节点，而不管处理节点是否被识别为来自I / O桥的中断消息分组中的目标。主机节点还从接收节点接收响应，并协调最低优先权仲裁。在固定的情况下，来自I / O桥的Extron或非向量中断消息，主机节点只需将中断包转发到系统中的所有其他节点，而不执行转换。处理器间中断也可以以类似的方式传送。中断响应与相应的中断消息分离，并且中断消息传递协议可以独立于承载中断分组的系统总线的物理属性来实现。

5. 发明授权

US06205508B1 Method for distributing interrupts in a multi-processor system 有权
标题翻译：在多处理器系统中分配中断的方法
公开(公告)号：US06205508B1
公开(公告)日：2001-03-20
申请号：US09251265
申请日：1999-02-16
申请人： Joseph A. Bailey , Norman M. Hack
发明人： Joseph A. Bailey , Norman M. Hack
IPC分类号： G06F1324
CPC分类号： G06F13/26
摘要： An interrupt messaging scheme for a multiprocessing computer system where a dedicated bus to carry interrupt messages within the multiprocessing system is eliminated. Instead, an interconnect structure using a plurality of high-speed dual-unidirectional links to interconnect processing nodes, I/O devices or I/O bridges in the system is implemented. Interrupt messages are transferred as discrete binary packets over point-to-point unidirectional links. Various interrupt requests are transferred through a predetermined set of discrete interrupt message packets. Interrupt message initiators—an I/O interrupt controller or a local interrupt controller (in case of an inter-processor interrupt)—may be configured to generate appropriate interrupt message packets upon receiving an interrupt request. A suitable routing algorithm may be employed to route various interrupt messages within the system. Simultaneous transmission of interrupt messages from two or more interrupt controllers may be possible without any need for bus arbitration. Interrupt response is decoupled from corresponding interrupt message and the interrupt messaging protocol may be implemented independently of the physical properties of a system bus carrying interrupt packets. System flexibility in managing interrupts is thus improved.
摘要翻译：用于多处理计算机系统的中断消息传递方案，其中消除了在多处理系统内携带中断消息的专用总线。相反，实现了使用多个高速双向链路来互连系统中的处理节点，I / O设备或I / O桥的互连结构。中断消息作为离散二进制数据包通过点对点单向链路传输。各种中断请求通过预定的一组离散中断消息包传送。中断信息发起者 - I / O中断控制器或本地中断控制器（在处理器间中断的情况下）可以被配置为在接收到中断请求时产生适当的中断消息包。可以采用合适的路由算法来路由系统内的各种中断消息。可以在不需要总线仲裁的情况下同时传输来自两个或多个中断控制器的中断消息。中断响应与相应的中断消息分离，并且中断消息传递协议可以独立于承载中断分组的系统总线的物理属性来实现。因此改善了管理中断的系统灵活性。

6. 发明授权

US06904545B1 Fault tolerant computing node having multiple host channel adapters 有权
标题翻译：具有多个主机通道适配器的容错计算节点
公开(公告)号：US06904545B1
公开(公告)日：2005-06-07
申请号：US09901683
申请日：2001-07-11
申请人： Bahadir Erimli , Joseph A. Bailey , Norman M. Hack
发明人： Bahadir Erimli , Joseph A. Bailey , Norman M. Hack
IPC分类号： G06F11/00
CPC分类号： H04L12/64 , G06F11/2007
摘要： A computing node configured for communications on an InfiniBand™ network includes at least two host channel adapters configured for communications on the InfiniBand™ network, and at least one processor configured for controlling the communications of the two host channel adapters on the InfiniBand™ network. The host channel adapters communicate with the processor via an internal bus. The processor monitors communication operations by the host channel adapters on the InfiniBand™ network. If the processor detects that one of the host channel adapters is unable to complete the corresponding communication operations, the processor outputs a message requesting traffic destined to the one host channel adapter to be redirected to the remaining host channel adapter.
摘要翻译：配置用于InfiniBand TM网络上的通信的计算节点包括配置用于InfiniBand TM网络上的通信的至少两个主机信道适配器，以及被配置用于控制InfiniBand上的两个主机信道适配器的通信的至少一个处理器（TM）网络。主机通道适配器通过内部总线与处理器进行通信。处理器监视InfiniBand（TM）网络上的主机通道适配器的通信操作。如果处理器检测到主机信道适配器中的一个无法完成相应的通信操作，则处理器输出请求流向一个主机信道适配器的流量的消息被重定向到剩余的主机信道适配器。

7. 发明授权

US5894578A System and method for using random access memory in a programmable interrupt controller 失效
标题翻译：在可编程中断控制器中使用随机存取存储器的系统和方法
公开(公告)号：US5894578A
公开(公告)日：1999-04-13
申请号：US575685
申请日：1995-12-19
申请人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
发明人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a central interrupt controller, random access memory, and at least one processor interface. The central interrupt controller systematically selects interrupt requests from the interrupt request interface. Information associated with each interrupt request is stored in the random access memory. The central interrupt controller access the information in the random access memory and uses the information and the state of the currently selected interrupt request to determine a next state for the currently selected interrupt request. The information is passed on to the processor interface to determine when and if the interrupt request should issue to one of the CPUs.
摘要翻译：提供了一种用于包括一个或多个CPU的计算机系统的可编程中断控制器。可编程中断控制器包括中断请求接口，中央中断控制器，随机存取存储器和至少一个处理器接口。中央中断控制器系统地从中断请求接口中选择中断请求。与每个中断请求相关联的信息存储在随机存取存储器中。中央中断控制器访问随机存取存储器中的信息，并使用当前选择的中断请求的信息和状态来确定当前选择的中断请求的下一状态。该信息被传递到处理器接口，以确定中断请求何时以及是否向其中一个CPU发布。

8. 发明授权

US5892956A Serial bus for transmitting interrupt information in a multiprocessing system 失效
标题翻译：用于在多处理系统中传输中断信息的串行总线
公开(公告)号：US5892956A
公开(公告)日：1999-04-06
申请号：US934261
申请日：1997-09-19
申请人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
发明人： Qadeer A. Qureshi , Joseph A. Bailey , Dan S. Mudgett
IPC分类号： G06F9/46 , G06F13/26
CPC分类号： G06F13/26
摘要： A programmable interrupt controller for use in a multiprocessing environment that can support a serial bus to send interrupt information to the processors. The interrupt serial bus has a data line to drive all the interrupt information to all the processors and a clock line to synchronize edges for the data stream. A third line, normally tri-stated, may be used to provide a parity error indication for the serial bus. The serial data includes a processor identification, a pin identification and state information. As the programmable interrupt controller sends the interrupt data on the serial bus, all the processors clock the data and check parity. If a processor finds a parity error, it drives the parity error indication low so that the information may be transmitted again. No processor will execute the command contained in the serial message before the time has elapsed for any of the processors to report a parity error. If there is no parity error, the processor accepts and decodes the message and asserts or deasserts the appropriate signal.
摘要翻译：一种用于多处理环境的可编程中断控制器，可以支持串行总线向处理器发送中断信息。中断串行总线具有数据线，用于将所有中断信息驱动到所有处理器和时钟线以同步数据流的边沿。通常三通道的第三行可用于为串行总线提供奇偶校验错误指示。串行数据包括处理器标识，引脚标识和状态信息。由于可编程中断控制器在串行总线上发送中断数据，所有的处理器都会对数据进行计时并检查奇偶校验。如果处理器发现奇偶校验错误，则将奇偶校验错误指示值驱动为低，以便再次发送信息。没有处理器将在任何处理器报告奇偶校验错误的时间过去之前执行包含在串行消息中的命令。如果没有奇偶校验错误，则处理器接受并解码消息，并声明或取消对相应信号的声明。

9. 发明授权

US5557769A Mechanism and protocol for maintaining cache coherency within an integrated processor 失效
标题翻译：用于在集成处理器内维护高速缓存一致性的机制和协议
公开(公告)号：US5557769A
公开(公告)日：1996-09-17
申请号：US261242
申请日：1994-06-17
申请人： Joseph A. Bailey , Steve L. Belt
发明人： Joseph A. Bailey , Steve L. Belt
IPC分类号： G06F12/08
CPC分类号： G06F12/0835
摘要： An integrated processor includes CPU core, cache memory, and cache controller coupled to a local bus via a local bus interface. The integrated processor further includes memory controller for coupling system memory to the local bus, and a bus interface unit for coupling external peripheral devices to the local bus. The cache controller includes an address tag and state logic circuit which keeps track of a physical address in system memory which corresponds to each entry within cache memory. Address tag and state logic circuit contains state information that indicates whether each cache line is valid and/or dirty. The cache controller includes a snoop control circuit which monitors the local bus to determine whether a memory cycle has been executed by an alternate bus master. During such a memory cycle of an alternate bus master, a comparator circuit determines whether a cache hit has occurred. If a cache read hit occurs with respect to a dirty cache line, the cache controller asserts an inhibit signal which causes the memory controller to ignore the cycle. The read request is instead serviced by the cache controller by providing the requested data from the cache memory to local bus 112. If a cache write operation occurs, data is written into the system memory via system memory controller, and the data is concurrently latched into the corresponding line of the cache memory. The status of cache line may further be updated to clean if the data transfer encompassed a complete cache line.
摘要翻译：集成处理器包括经由本地总线接口耦合到本地总线的CPU内核，高速缓冲存储器和高速缓存控制器。集成处理器还包括用于将系统存储器耦合到本地总线的存储器控制器，以及用于将外部外围设备耦合到本地总线的总线接口单元。高速缓存控制器包括地址标签和状态逻辑电路，其跟踪与高速缓冲存储器内的每个条目对应的系统存储器中的物理地址。地址标签和状态逻辑电路包含指示每个高速缓存行是否有效和/或脏的状态信息。高速缓存控制器包括一个监视控制电路，监视本地总线，以确定一个存储器周期是否由一个备用总线主机执行。在替代总线主机的这种存储周期期间，比较器电路确定是否发生了高速缓存命中。如果相对于脏高速缓存线发生缓存读取命中，则高速缓存控制器断言禁止信号，这导致存储器控制器忽略该周期。读取请求由高速缓存控制器通过从缓存存储器向本地总线112提供所请求的数据而被服务。如果发生高速缓存写入操作，则通过系统存储器控制器将数据写入系统存储器，并且数据被同时锁存高速缓存的相应行。如果数据传输包含完整的高速缓存行，则可以进一步更新高速缓存行的状态以进行清理。

10. 发明授权

US06742075B1 Arrangement for instigating work in a channel adapter based on received address information and stored context information 有权
标题翻译：基于收到的地址信息和存储的上下文信息，在通道适配器中启动工作的安排
公开(公告)号：US06742075B1
公开(公告)日：2004-05-25
申请号：US09998187
申请日：2001-12-03
申请人： Joseph A. Bailey , Joseph Winkles
发明人： Joseph A. Bailey , Joseph Winkles
IPC分类号： G06F1336
CPC分类号： G06F13/14
摘要： A host channel adapter is configured for servicing a work notification, supplied by a host process to an assigned destination address accessable by the host channel adapter, based on matching the assigned destination address with a stored notification address from one of a plurality of queue pair context entries stored within the host channel adapter. The host channel adapter receives a queue pair context entry including a notification address, based on creation of a corresponding queue pair for a host process. The queue pair enables the host process to post a work descriptor and output a work notification to the host channel adapter by writing the work notification to an assigned destination address. The host channel adapter matches the assigned destination address with a stored notification address, and services the work descriptor based on the corresponding queue pair attributes specified in the identified queue pair context entry.
摘要翻译：主机通道适配器被配置为基于将所分配的目的地地址与从多个队列对上下文之一的存储的通知地址相匹配来将由主机进程提供的工作通知服务到由主机通道适配器可访问的分配的目的地地址存储在主机通道适配器内的条目。主机通道适配器基于为主机进程创建相应的队列对，接收包括通知地址的队列对上下文条目。队列对使主机进程能够发布工作描述符，并通过将工作通知写入分配的目的地地址来向主机通道适配器输出工作通知。主机通道适配器将分配的目的地地址与存储的通知地址相匹配，并且基于在所识别的队列对上下文条目中指定的对应的队列对属性来服务于工作描述符。

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