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    • 4. 发明申请
    • Hetero-Junction Tunneling Transistor
    • 异质结隧道晶体管
    • US20120298960A1
    • 2012-11-29
    • US13479392
    • 2012-05-24
    • Osama M. NayfehMadan Dubey
    • Osama M. NayfehMadan Dubey
    • H01L29/775
    • H01L29/0847H01L29/7391
    • A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that a portion of the second layer overlies the first layer and forms the drain for the transistor. An insulating layer and metallic gate for the transistor is deposited on top of the second layer so that the gate is aligned with the overlying portions of the first and second layers. The gate voltage controls the conduction between the source and the drain and the conduction between the first and second layers occurs by vertical tunneling between the layers.
    • 异质结隧道晶体管具有第一层p ++硅锗,其在一端形成晶体管的源极。 沉积第二层n +硅材料,使得第二层的一部分覆盖第一层并形成晶体管的漏极。 用于晶体管的绝缘层和金属栅极沉积在第二层的顶部上,使得栅极与第一层和第二层的上覆部分对准。 栅极电压控制源极和漏极之间的导通,并且第一和第二层之间的导通通过层之间的垂直隧道发生。
    • 10. 发明授权
    • Hetero-junction tunneling transistor
    • 异质结隧道晶体管
    • US08629480B2
    • 2014-01-14
    • US13479392
    • 2012-05-24
    • Osama M. NayfehMadan Dubey
    • Osama M. NayfehMadan Dubey
    • H01L29/66
    • H01L29/0847H01L29/7391
    • A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that a portion of the second layer overlies the first layer and forms the drain for the transistor. An insulating layer and metallic gate for the transistor is deposited on top of the second layer so that the gate is aligned with the overlying portions of the first and second layers. The gate voltage controls the conduction between the source and the drain and the conduction between the first and second layers occurs by vertical tunneling between the layers.
    • 异质结隧道晶体管具有第一层p ++硅锗,其在一端形成晶体管的源极。 沉积第二层n +硅材料,使得第二层的一部分覆盖第一层并形成晶体管的漏极。 用于晶体管的绝缘层和金属栅极沉积在第二层的顶部上,使得栅极与第一层和第二层的上覆部分对准。 栅极电压控制源极和漏极之间的导通,并且第一和第二层之间的导通通过层之间的垂直隧道发生。