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1. 发明授权

US08139069B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08139069B1
公开(公告)日：2012-03-20
申请号：US11556660
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

2. 发明授权

US08379033B2 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08379033B2
公开(公告)日：2013-02-19
申请号：US13399458
申请日：2012-02-17
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

3. 发明申请

US20120147027A1 METHOD AND SYSTEM FOR IMPROVING DATA COHERENCY IN A PARALLEL RENDERING SYSTEM 有权
标题翻译：用于提高并行渲染系统中的数据相关性的方法和系统
公开(公告)号：US20120147027A1
公开(公告)日：2012-06-14
申请号：US13399458
申请日：2012-02-17
申请人： Steven E. MOLNAR , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. MOLNAR , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

4. 发明授权

US08085272B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08085272B1
公开(公告)日：2011-12-27
申请号：US11556657
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性公共输入流。每个片段流被独立地处理并对应于其中一个ROP请求流。

5. 发明授权

US06959110B1 Multi-mode texture compression algorithm 有权
标题翻译：多模纹理压缩算法
公开(公告)号：US06959110B1
公开(公告)日：2005-10-25
申请号：US09929427
申请日：2001-08-13
申请人： John M. Danskin , Gary M. Tarolli , Murali Sundaresan
发明人： John M. Danskin , Gary M. Tarolli , Murali Sundaresan
IPC分类号： G06K9/00
CPC分类号： H04N19/428 , H04N19/12 , H04N19/136 , H04N19/186 , H04N19/426
摘要： A multi-mode texture compression algorithm is provided for effective compression and decompression texture data during graphics processing. Initially, a request is sent to memory for compressed texture data. Such compressed texture data is then received from the memory in response to the request. At least one of a plurality of compression algorithms associated with the compressed texture data is subsequently identified. Thereafter, the compressed texture data is decompressed in accordance with the identified compression algorithm.
摘要翻译：提供了多模式纹理压缩算法，用于在图形处理期间有效地压缩和解压缩纹理数据。最初，向存储器发送压缩纹理数据的请求。响应于该请求，然后从存储器接收这样的压缩纹理数据。随后识别与压缩纹理数据相关联的多个压缩算法中的至少一个。此后，根据所识别的压缩算法对压缩的纹理数据进行解压缩。

6. 发明授权

US07508398B1 Transparent antialiased memory access 有权
标题翻译：透明抗锯齿存储器访问
公开(公告)号：US07508398B1
公开(公告)日：2009-03-24
申请号：US10646076
申请日：2003-08-22
申请人： John S. Montrym , Brian D. Hutsell , Steven E. Molnar , Gary M. Tarolli , Christopher T. Cheng , Emmett M. Kilgariff , Abraham B. de Waal
发明人： John S. Montrym , Brian D. Hutsell , Steven E. Molnar , Gary M. Tarolli , Christopher T. Cheng , Emmett M. Kilgariff , Abraham B. de Waal
IPC分类号： G06F12/10 , G09G5/36 , G09G5/00
CPC分类号： G06T1/60 , G09G5/363 , G09G5/393 , G09G2320/02 , G09G2340/10 , G09G2360/18
摘要： A system and method for providing antialiased memory access includes receiving a request to access a memory address. The memory address is examined to determine if the memory address is within a virtual frame buffer. If the memory address is within a virtual frame buffer then the memory address is transformed into one or more physical addresses within a frame buffer that is utilized for antialiasing. The frame buffer may be a single memory space containing subpixel information corresponding to pixels of the virtual frame buffer. Subpixels located at the physical addresses within the frame buffer are then accessed. The disclosed invention provides for direct access by a software application.
摘要翻译：用于提供抗混叠存储器访问的系统和方法包括接收访问存储器地址的请求。检查存储器地址以确定存储器地址是否在虚拟帧缓冲器内。如果存储器地址在虚拟帧缓冲器内，则存储器地址被转换为用于抗锯齿的帧缓冲器内的一个或多个物理地址。帧缓冲器可以是包含对应于虚拟帧缓冲器的像素的子像素信息的单个存储器空间。然后访问位于帧缓冲器内的物理地址的子像素。所公开的发明提供了软件应用程序的直接访问。

7. 发明授权

US07852340B2 Scalable shader architecture 有权
标题翻译：可扩展着色器架构
公开(公告)号：US07852340B2
公开(公告)日：2010-12-14
申请号：US11957358
申请日：2007-12-14
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
IPC分类号： G06F15/80 , G06T15/50 , G06T15/00
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

8. 发明授权

US07385607B2 Scalable shader architecture 有权
标题翻译：可扩展着色器架构
公开(公告)号：US07385607B2
公开(公告)日：2008-06-10
申请号：US10938042
申请日：2004-09-10
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
IPC分类号： G06F15/16 , G06F15/80 , G06T1/20
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译：公开了可扩展着色器架构。根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。

9. 发明授权

US5657047A Method and apparatus for zooming images on a video display 失效
标题翻译：用于在视频显示器上放大图像的方法和装置
公开(公告)号：US5657047A
公开(公告)日：1997-08-12
申请号：US386742
申请日：1995-02-10
申请人： Gary M. Tarolli
发明人： Gary M. Tarolli
IPC分类号： G06T3/40 , G09G5/393 , G09G5/00
CPC分类号： G06T3/40 , G09G5/393
摘要： An apparatus and method for enlarging a source image on a computer display is described. A scanline buffer stores pixels in a first row of the source image. Coordination circuitry receives from a processor and stores pixels in a second row of the source image. Blend circuitry generates output pixels, such that each of the output pixels corresponds to a weighted average of a plurality of input pixels. The plurality of input pixels comprises two pixels stored in the scanline buffer and two pixels stored in the coordination circuitry. Control circuitry determines weight values and provides the weight values to the blend circuitry for calculating the weighted average. The control circuitry also determines, based on the weight values, which pixels stored in the scanline buffer and in the coordination circuitry are used by the blend circuitry as the input pixels. In addition, the control circuitry replaces the pixels in the scanline buffer with corresponding pixels from the coordination circuitry after the last time the pixels in the scanline buffer are used as the input pixels.
摘要翻译：描述了用于在计算机显示器上放大源图像的装置和方法。扫描线缓冲器存储源图像的第一行中的像素。协调电路从处理器接收并存储源图像的第二行中的像素。混合电路产生输出像素，使得每个输出像素对应于多个输入像素的加权平均。多个输入像素包括存储在扫描线缓冲器中的两个像素和存储在协调电路中的两个像素。控制电路确定权重值，并为混合电路提供权重值以计算加权平均值。控制电路还基于权重值确定存储在扫描线缓冲器和协调电路中的哪些像素被混合电路用作输入像素。此外，控制电路在最后一次使用扫描线缓冲器中的像素作为输入像素之后，用扫描线缓冲器中的像素替代来自协调电路的相应像素。

10. 发明授权

US07949855B1 Scheduler in multi-threaded processor prioritizing instructions passing qualification rule 有权
标题翻译：多线程处理器调度器优先级指令通过资格规则
公开(公告)号：US07949855B1
公开(公告)日：2011-05-24
申请号：US12110942
申请日：2008-04-28
申请人： Peter C. Mills , John Erik Lindholm , Brett W. Coon , Gary M. Tarolli , John Matthew Burgess
发明人： Peter C. Mills , John Erik Lindholm , Brett W. Coon , Gary M. Tarolli , John Matthew Burgess
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/3853 , G06F9/3867 , G06F9/3885
摘要： A processor buffers asynchronous threads. Instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one computation operation and at least one memory access operation. Instructions within each phase are qualified and prioritized. The instructions may be qualified based on the status of the execution unit needed to execute one or more of the current instructions. The instructions may also be qualified based on an age of each instruction, status of the execution units, a divergence potential, locality, thread diversity, and resource requirements. Qualified instructions may be prioritized based on execution units needed to execute instructions and the execution units in use. One or more of the prioritized instructions is issued per cycle to the plurality of execution units.
摘要翻译：处理器缓冲异步线程。由多个执行单元提供的需要操作的指令被划分为相位，每个阶段具有至少一个计算操作和至少一个存储器访问操作。每个阶段的说明是合格的，并且是优先考虑的。可以基于执行一个或多个当前指令所需的执行单元的状态来限制指令。指令也可以基于每个指令的年龄，执行单元的状态，发散电位，局部性，线程分集和资源需求来限定。可以根据执行指令所需的执行单元和正在使用的执行单元来优先确定合格的指令。每个周期向多个执行单元发出一个或多个优先指令。

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