专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5990557A Bias plasma deposition for selective low dielectric insulation 失效
标题翻译：偏压等离子体沉积用于选择性低介电绝缘
公开(公告)号：US5990557A
公开(公告)日：1999-11-23
申请号：US964430
申请日：1997-11-04
申请人： Steven Avanzino , Darrell M. Erb , Robin Cheung , Rich Klein , Pervaiz Sultan
发明人： Steven Avanzino , Darrell M. Erb , Robin Cheung , Rich Klein , Pervaiz Sultan
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/485
CPC分类号： H01L21/02164 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/31612 , H01L21/7682 , H01L21/76837 , H01L23/5222 , H01L2924/0002
摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with void free insulating material with a dielectric constant of greater than about 3.5.
摘要翻译：在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别通过沉积具有差的绝缘材料的步进功能的非共形源（例如硅烷）而具有约0.5微米或更小的间隙（SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在0.5微米或更小的空隙形成之后间隙，沉积的非共形材料与沉积同时或顺序蚀刻，以用无空隙绝缘填充剩余的间隙。沉积的绝缘材料的表面被平坦化为所需的厚度。或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。所形成的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，其中间隔为0.5或更小的导电线对之间的绝缘体的介电常数与空隙结合为至少约3或较低，并且所有剩余的间隙都填充有绝缘材料，介电常数大于约3.5。

2. 发明授权

US5776834A Bias plasma deposition for selective low dielectric insulation 失效
公开(公告)号：US5776834A
公开(公告)日：1998-07-07
申请号：US478315
申请日：1995-06-07
申请人： Steven Avanzino , Darrell M. Erb , Robin Cheung , Rich Klein , Pervaiz Sultan
发明人： Steven Avanzino , Darrell M. Erb , Robin Cheung , Rich Klein , Pervaiz Sultan
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L21/471
CPC分类号： H01L21/02164 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/31612 , H01L21/7682 , H01L21/76837 , H01L23/5222 , H01L2924/0002
摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with void free insulating material with a dielectric constant of greater than about 3.5.

3. 发明授权

US5691573A Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines 失效
标题翻译：在狭窄的空间分离导线的介电常数小于3的复合绝缘
公开(公告)号：US5691573A
公开(公告)日：1997-11-25
申请号：US481030
申请日：1995-06-07
申请人： Steven Avanzino , Darrell M. Erb , Robin Cheung , Rich Klein
发明人： Steven Avanzino , Darrell M. Erb , Robin Cheung , Rich Klein
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/485 , H01L23/52
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L23/53295 , H01L2924/0002
摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with the gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.
摘要翻译：在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷（SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在所有导电线都已经接收到保形膜绝缘材料和可流动的绝缘材料，优选通过蚀刻从具有约0.5微米或更小的间隙的那对导电线去除复合绝缘材料。现在，沉积具有差的阶梯函数的非共形绝缘材料，并且在0.5微米或更小的开放间隙中产生大的空隙。在形成空隙之后，沉积继续并且在所需的绝缘复合厚度下被平坦化。或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。所得到的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，导电线对之间的绝缘介电常数为0.5或更小的间隙，与空隙结合为至少约3 或更低，并且所有剩余间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

4. 发明授权

US6048802A Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines 失效
标题翻译：在某些导电线之间形成低介电绝缘的选择性非共形沉积
公开(公告)号：US6048802A
公开(公告)日：2000-04-11
申请号：US905978
申请日：1997-08-05
申请人： Steven Avanzino , Darrell Erb , Robin Cheung , Rich Klein
发明人： Steven Avanzino , Darrell Erb , Robin Cheung , Rich Klein
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/441
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L23/53295 , H01L2924/0002
摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with the gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.
摘要翻译：在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷（SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在所有导电线都已经接收到保形膜绝缘材料和可流动的绝缘材料，优选通过蚀刻从具有约0.5微米或更小的间隙的那对导电线去除复合绝缘材料。现在，沉积具有差的阶梯函数的非共形绝缘材料，并且在0.5微米或更小的开放间隙中产生大的空隙。在形成空隙之后，沉积继续并且在所需的绝缘复合厚度下被平坦化。或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。所得到的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，导电线对之间的绝缘介电常数为0.5或更小的间隙，与空隙结合为至少约3 或更低，并且所有剩余间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

5. 发明授权

US5955786A Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines 失效
标题翻译：半导体器件使用均匀的非共形沉积法在某些导线之间形成低介电常数绝缘
公开(公告)号：US5955786A
公开(公告)日：1999-09-21
申请号：US481906
申请日：1995-06-07
申请人： Steven Avanzino , Darrell Erb , Robin Cheung , Rich Klein
发明人： Steven Avanzino , Darrell Erb , Robin Cheung , Rich Klein
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02211 , H01L21/02216 , H01L21/02271 , H01L21/02274 , H01L21/02282 , H01L21/31612 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002
摘要： A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposition of the nonconformal source material is stopped and a flowable insulating material, such as spin on glass, is coated on nonconformal insulating material to fill the remaining gaps. After etching the surfaces of the nonconformal and flowable insulating materials, another insulating layer is deposited and planarized to the desired overall thickness of the insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and substantially all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.
摘要翻译：在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷（SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在0.5微米或更小的空隙形成之后间隙，停止非共形源材料的沉积，并且将可流动的绝缘材料（例如玻璃上的旋涂）涂覆在非共形绝缘材料上以填充剩余的间隙。在蚀刻非共形和可流动的绝缘材料的表面之后，另外的绝缘层被沉积并平坦化到所需绝缘体的总厚度。或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。所形成的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，其中间隔为0.5或更小的导电线对之间的绝缘体的介电常数与空隙结合为至少约3或较低且基本上所有剩余的间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

6. 发明授权

US5614765A Self aligned via dual damascene 失效
标题翻译：通过双镶嵌自对准
公开(公告)号：US5614765A
公开(公告)日：1997-03-25
申请号：US478319
申请日：1995-06-07
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L2221/1036 , H01L2924/0002
摘要： An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.
摘要翻译：用于集成电路和用于半导体器件的衬底载体的绝缘分隔的导线和连接通孔的互连级别，使用双镶嵌仅具有一个掩模图案以形成导电线和通孔。导电线的掩模图案包含在绝缘材料中要形成通孔开口的横向扩大区域。在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于绝缘材料到其附魔。保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。侧壁用作通过开口蚀刻的自对准掩模。保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。在后者中，导电线路开口和通孔用相同的导电材料填充。

7. 发明授权

US6051882A Subtractive dual damascene semiconductor device 失效
标题翻译：减法双镶嵌半导体器件
公开(公告)号：US6051882A
公开(公告)日：2000-04-18
申请号：US905974
申请日：1997-08-05
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Rin Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Rin Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/52
CPC分类号： H01L23/5226 , H01L21/76807 , H01L21/76813 , H01L21/76877 , H01L21/76885 , H01L2924/0002
摘要： A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.
摘要翻译：一种制造导线的互连电平的方法，以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法，其使用反向镶嵌来形成导电线和通孔。首先使用导电线图案来完全蚀刻该层以形成导电线开口。开口完全被导电材料填充并平坦化，使得导电材料和绝缘层的表面是共面的。通孔图案垂直于导电线对齐，并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。由此在导电线的上部形成的开口用绝缘材料填充，以完成与绝缘层下部的导电线和层的上部向上突出的通孔的双镶嵌互连水平。此外，通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。所产生的互连级联结构包括具有向上和向下突出的通孔的导线。

8. 发明授权

US5686354A Dual damascene with a protective mask for via etching 失效
标题翻译：双镶嵌带防蚀口罩，用于通孔蚀刻
公开(公告)号：US5686354A
公开(公告)日：1997-11-11
申请号：US478324
申请日：1995-06-07
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76831 , H01L21/76807
摘要： A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material. If the protective material is an insulating material, it is entirely removed before filling the conductive line and via openings conductive material.
摘要翻译：一种双镶嵌方法，用于制造导线的互连级别并且连接用于集成电路的绝缘和用于半导体器件的衬底载体的通孔，其使用薄的保护性通孔掩模形成通孔。导电线掩模图案用于在绝缘层中形成导电线路开口。接下来，在导电线路开口中沉积有保形材料的薄保护层。保护层和绝缘层各自具有对其它蚀刻剂的耐蚀刻性。使用通孔掩模图案，开口蚀刻保护层，绝缘层用作蚀刻停止。接下来通过开口被蚀刻在绝缘材料中，使用薄保护层中的开口作为蚀刻掩模。如果保护层是导电材料，则在导电线之前或之后将其从绝缘层的表面去除，并且通孔开口填充有导电材料。如果保护材料是绝缘材料，则在填充导电线和通孔开口导电材料之前将其完全去除。

9. 发明授权

US5795823A Self aligned via dual damascene 失效
标题翻译：通过双镶嵌自对准
公开(公告)号：US5795823A
公开(公告)日：1998-08-18
申请号：US752807
申请日：1996-11-20
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L21/441
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L2221/1036 , H01L2924/0002
摘要： A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.
摘要翻译：一种用于集成电路和用于半导体器件的衬底载体的绝缘体分隔开的导线的连接通孔和通孔的方法，其中使用双镶嵌仅具有一个用于形成导电线和通孔的掩模图案。导电线的掩模图案包含在绝缘材料中要形成通孔开口的横向扩大区域。在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于绝缘材料到其附魔。保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。侧壁用作通过开口蚀刻的自对准掩模。保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。在后者中，导电线路开口和通孔用相同的导电材料填充。

10. 发明授权

US5705430A Dual damascene with a sacrificial via fill 失效
标题翻译：双镶嵌与牺牲通过填充
公开(公告)号：US5705430A
公开(公告)日：1998-01-06
申请号：US486777
申请日：1995-06-07
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76808 , H01L2221/1031
摘要： A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and, preferably, is substantially higher than second layer. Using a conductive line pattern aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings. In a second embodiment, the sacrificial material is not etchable by the etchant for forming the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which the first insulating layer is resistive or less selective. A conductive material now is deposited in the conductive line and via openings.
摘要翻译：一种双镶嵌方法，用于制造用于集成电路的绝缘体分隔开的导电线路的互连电平和用于半导体器件的衬底载体的通孔，其使用牺牲通孔填充物。第一层绝缘材料形成有通孔。开口填充有牺牲可移除材料。在第一层上放置第二层绝缘材料。在一个实施例中，对第二层的蚀刻剂的蚀刻选择性基本上与牺牲通孔填充相同，并且优选地基本上高于第二层。使用与通孔开口对准的导电线图案，在第二绝缘层中蚀刻导电线开口，并且在蚀刻期间，将牺牲填充物从通孔开口移除。在第二实施例中，牺牲材料不可蚀刻用于形成导电线路开口的蚀刻剂，并且在形成导电线路开口之后，用第一绝缘层具有电阻或较小选择性的蚀刻剂去除牺牲材料。导电材料现在沉积在导电线和通孔中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式