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1. 发明授权

US07531086B2 Pressure filter apparatus 失效
标题翻译：压滤机
公开(公告)号：US07531086B2
公开(公告)日：2009-05-12
申请号：US10504608
申请日：2003-02-13
申请人： Steve C. Benesi , Patrick J. Costelloe , Anthony C. Miller
发明人： Steve C. Benesi , Patrick J. Costelloe , Anthony C. Miller
IPC分类号： B01D25/127
CPC分类号： B01D25/1275 , B01D25/172 , B01D25/325 , B01D29/093 , B01D29/096 , B01D29/684
摘要： A pressure filter apparatus is shown and disclosed with a construction that permits the filter to be operated to produce food grade or pharmaceutical grade products where there are requirements for periodic cleaning, sterilizing or sanitizing of the apparatus. The structures of the filter apparatus are sloped or clad to drain any fluids away from the apparatus. The exterior can be washed in place and the interior can be washed with the exterior washing or can be operated with internal washing cycles.
摘要翻译：示出和公开了一种压力过滤装置，其结构是允许过滤器操作以生产食品级或药用级产品，其中需要定期清洁，灭菌或消毒该设备。过滤装置的结构是倾斜的或包层的，以排出远离设备的任何流体。外部可以在适当位置进行洗涤，内部可以用外部洗涤剂洗涤，也可以在内部洗涤循环下进行操作。

2. 发明授权

US5889408A Delta IDDQ testing 失效
标题翻译： Delta IDDQ测试
公开(公告)号：US5889408A
公开(公告)日：1999-03-30
申请号：US670545
申请日：1996-06-27
申请人： Anthony C. Miller
发明人： Anthony C. Miller
IPC分类号： G01R31/30 , G01R31/28
CPC分类号： G01R31/3004 , G01R31/3008
摘要： A method for IDDQ testing to detect defects in a semiconductor device in the presence of a high background leakage current. In one embodiment at least a portion of a semiconductor device is biased and a first quiescent current measurement is taken. The portion of the semiconductor device that was biased is then unbiased and a second quiescent current measurement is taken. The first and second quiescent currents are then compared to determine if a defect exists in that portion of the semiconductor device.
摘要翻译：一种用于IDDQ测试的方法，用于在存在高背景漏电流的情况下检测半导体器件中的缺陷。在一个实施例中，半导体器件的至少一部分被偏置并且进行第一静态电流测量。然后偏置的半导体器件的部分是无偏置的，并且进行第二静态电流测量。然后比较第一和第二静态电流以确定半导体器件的该部分中是否存在缺陷。

3. 发明授权

US06215534B1 Aligning electro-optic material having standoffs formed from a fourth or higher metal interconnection layer 有权
标题翻译：对准具有由第四或更高金属互连层形成的间隔的电光材料
公开(公告)号：US06215534B1
公开(公告)日：2001-04-10
申请号：US09283337
申请日：1999-03-31
申请人： Kannan Raj , Oleg Rashkovskiy , Anthony C. Miller
发明人： Kannan Raj , Oleg Rashkovskiy , Anthony C. Miller
IPC分类号： G02F11333
CPC分类号： G02F1/13394 , G02F1/134363 , G02F2201/124 , G02F2201/128
摘要： An electro-optical device may include two pairs of electrodes which apply electric fields oriented at an angle with respect to one another. In this way, a second electric field may be used to create an alignment effect in the electro-optic material which normally is achieved using specially prepared alignment structures. The need for the alignment structures may be reduced or eliminated. The second electric field may be applied, for example, using metallic standoffs which space a top plate from a lower substrate and define a region for the electro-optic material. In this way, in large arrays, the electric field may be applied from a plurality of points improving the uniformity of the applied electric field. In smaller arrays, the field may be applied, for example, using peripheral electrodes.
摘要翻译：电光器件可以包括两对电极，其施加相对于彼此成一定角度定向的电场。以这种方式，可以使用第二电场来在电光材料中产生通常使用特别制备的对准结构来实现的对准效果。可以减少或消除对准结构的需要。第二电场可以例如使用将顶板从下基板空间并且限定电光材料的区域的金属支座施加。以这种方式，在大阵列中，可以从多个点施加电场，改善所施加的电场的均匀性。在较小的阵列中，例如可以使用外围电极施加该场。

4. 发明授权

US06278428B1 Display panel 有权
标题翻译：显示面板
公开(公告)号：US06278428B1
公开(公告)日：2001-08-21
申请号：US09275615
申请日：1999-03-24
申请人： Ronald D. Smith , Anthony C. Miller
发明人： Ronald D. Smith , Anthony C. Miller
IPC分类号： G09G336
CPC分类号： G09G3/3659 , G09G2300/0814 , G09G2310/04
摘要： A system includes an array of pixel cells, column lines, storage elements and decoding circuitry. The pixel cells are arranged in rows and columns and the column lines are associated with the column pixel cells. The storage elements are associated with a row of the pixel cells. The decoding circuitry is adapted to storage charges on the column lines and after the storage, transfer the charges from the column lines to the storage elements.
摘要翻译：系统包括像素单元，列线，存储元件和解码电路的阵列。像素单元以行和列排列，并且列线与列像素单元相关联。存储元件与像素单元的行相关联。解码电路适于在列线上存储电荷，并且在存储之后，将电荷从列线传送到存储元件。

5. 发明授权

US06239605B1 Method to perform IDDQ testing in the presence of high background leakage current 失效
标题翻译：在存在高背景泄漏电流的情况下执行IDDQ测试的方法
公开(公告)号：US06239605B1
公开(公告)日：2001-05-29
申请号：US09162912
申请日：1998-09-29
申请人： Anthony C. Miller
发明人： Anthony C. Miller
IPC分类号： G01R3100
CPC分类号： G01R31/3004 , G01R31/3008
摘要： A method for IDDQ testing to detect defects in a semiconductor device in the presence of a high background leakage current. At least a portion of a semiconductor device is biased and a first quiescent current measurement is taken. The measured portion of the semiconductor device is then unbiased and a second quiescent current measurement is taken. The first and second quiescent currents are then compared to determine if a defect exists in the tested portion of the semiconductor device.
摘要翻译：一种用于IDDQ测试的方法，用于在存在高背景漏电流的情况下检测半导体器件中的缺陷。半导体器件的至少一部分被偏置并且进行第一静态电流测量。然后半导体器件的测量部分是无偏置的，并且进行第二静态电流测量。然后比较第一和第二静态电流以确定在半导体器件的测试部分中是否存在缺陷。

6. 发明授权

US06239606B1 Method to perform IDDQ testing in the presence of high background leakage current 失效
标题翻译：在存在高背景泄漏电流的情况下执行IDDQ测试的方法
公开(公告)号：US06239606B1
公开(公告)日：2001-05-29
申请号：US09163592
申请日：1998-09-29
申请人： Anthony C. Miller
发明人： Anthony C. Miller
IPC分类号： G01R3128
CPC分类号： G01R31/3004 , G01R31/3008
摘要： A method for IDDQ testing to detect defects in a semiconductor integrated circuit in the presence of a high background leakage current is disclosed. In one embodiment of the present invention at least a portion of the semiconductor device is biased and first, second and third quiescent currents are measured and the currents are then compared. A defect in the circuit will show up as a high quiescent current for one or more of the biasing conditions. In a practical device many test patterns are required, for instance 200 patterns may be necessary to reveal defects. Additionally, the delta in current which is sought to detect the defect may need to be repeated several times to assure its detection.
摘要翻译：公开了一种用于在存在高背景泄漏电流的情况下检测半导体集成电路中的缺陷的IDDQ测试方法。在本发明的一个实施例中，半导体器件的至少一部分被偏置，并且测量第一，第二和第三静态电流，然后比较电流。对于一个或多个偏置条件，电路中的缺陷将显示为高静态电流。在实用的设备中，需要许多测试图案，例如可能需要200个图案来显示缺陷。此外，要检测缺陷的电流增量可能需要重复几次以确保其检测。

7. 发明授权

US5990699A Method for detecting opens through time variant current measurement 失效
标题翻译：检测方法通过时变电流测量打开
公开(公告)号：US5990699A
公开(公告)日：1999-11-23
申请号：US587088
申请日：1996-01-16
申请人： Anthony C. Miller , Wayne M. Needham
发明人： Anthony C. Miller , Wayne M. Needham
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/026 , G01R31/2621
摘要： A method for detecting open circuits in a semiconductor device, more specifically in a static CMOS device. A device to be tested is powered-up and the clock on the device is stopped so that the device enters a quiescent state. Once the device has reached a quiescent state a first current is measured and after a specified period of time a second current is also measured. The first current and the second current are then compared to determine if there is a defect, i.e. an open circuit, in the device. The determination as to whether or not a device is defective is based upon the difference between the first and second current measurements.
摘要翻译：一种用于检测半导体器件中的开路的方法，更具体地，在静态CMOS器件中。要测试的器件上电，器件上的时钟停止工作，使器件进入静态状态。一旦器件达到静态状态，测量第一个电流，并且在指定的时间段之后还测量第二个电流。然后比较第一电流和第二电流，以确定器件中是否存在缺陷（即开路）。关于设备是否有故障的确定是基于第一和第二电流测量之间的差异。

8. 发明授权

US06980183B1 Liquid crystal over semiconductor display with on-chip storage 失效
标题翻译：半导体显示器上的液晶在片上存储
公开(公告)号：US06980183B1
公开(公告)日：2005-12-27
申请号：US09365363
申请日：1999-07-30
申请人： Scott A. Rosenberg , Anthony C. Miller
发明人： Scott A. Rosenberg , Anthony C. Miller
IPC分类号： G06F13/14 , G09G3/36
CPC分类号： G09G3/3648 , G09G2300/0809 , G09G2300/0842
摘要： A display device, such as a projector system, may include a plurality of display panels formed from liquid crystal over semiconductor substrates which incorporate not only the pixel elements but memory as well. The presence of memory in the display allows a host system, such as a computer, to send only new picture information to the display and avoid the transmission of information that does not change. Thus, the display update bandwidth required of the host system may be reduced, allowing the host system to use resources typically required by the display update process for improved performance of other operations. In addition, the elimination of redundant information being transmitted to the display may allow more new information to be transmitted, enabling, for example, a higher resolution display.
摘要翻译：诸如投影仪系统的显示装置可以包括由半导体衬底上的液晶形成的多个显示面板，其不仅包括像素元件，而且包括存储器。存储器在显示器中的存在允许诸如计算机的主机系统仅向显示器发送新的图像信息，并避免不改变的信息的传输。因此，可以减少主机系统所需的显示更新带宽，从而允许主机系统使用通常由显示更新处理所需的资源来改善其他操作的性能。此外，消除正在发送到显示器的冗余信息可以允许发送更多新的信息，使得能够例如更高分辨率的显示。

9. 发明授权

US06208392B1 Metallic standoff for an electro-optical device formed from a fourth or higher metal interconnection layer 有权
标题翻译：用于由第四或更高金属互连层形成的电光器件的金属间隔
公开(公告)号：US06208392B1
公开(公告)日：2001-03-27
申请号：US09258226
申请日：1999-02-26
申请人： Anthony C. Miller , Kannan Raj
发明人： Anthony C. Miller , Kannan Raj
IPC分类号： G02F11333
CPC分类号： G02F1/136227 , G02F1/136277
摘要： An electro-optical device may be defined using metallic standoffs between a top plate and a substrate, such as a silicon substrate in a liquid crystal on silicon (LCOS) technology. In one embodiment, the metallic standoffs may be formed from a metal layer, such as metal four layer, above the metal layer used to form the metal pixel mirrors. In this way, relatively constant and uniform cell thicknesses may be achieved without significantly increasing the processing overhead.
摘要翻译：可以使用在液晶硅（LCOS）技术中的顶板和衬底（例如硅衬底）之间的金属支座来限定电光器件。在一个实施例中，金属支座可以由用于形成金属像素镜的金属层之上的金属层（例如金属四层）形成。以这种方式，可以实现相对恒定和均匀的电池厚度，而不显着增加处理开销。

10. 发明授权

US6055656A Control register bus access through a standardized test access port 失效
标题翻译：控制寄存器总线访问通过标准化测试访问端口
公开(公告)号：US6055656A
公开(公告)日：2000-04-25
申请号：US434163
申请日：1995-05-02
申请人： James A. Wilson, Jr. , Anthony C. Miller , Michael W. Rhodehamel , Adrian Carbine , Derek B. I. Feltham , Sumeet Agrawal
发明人： James A. Wilson, Jr. , Anthony C. Miller , Michael W. Rhodehamel , Adrian Carbine , Derek B. I. Feltham , Sumeet Agrawal
IPC分类号： G01R31/3185 , G06F11/267 , G01R31/28
CPC分类号： G06F11/2236 , G01R31/318572
摘要： A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.
摘要翻译：用于通过配置成建立的测试标准的测试访问端口访问控制寄存器总线和微处理器的控制寄存器的方案。微处理器的测试访问端口（TAP）被配置为基于IEEE 1149.1标准中规定的技术来串行地进行通信。外部串行指令被转换为并行传输，以提供用于访问内部结构的控制信号。串行地址和数据信号也被转换为并行传输以访问控制寄存器总线上的内部结构，并行输出转换为用于外部输出的串行格式。通过允许外部访问低级内部总线架构，可以通过利用外部编程来执行系统测试和调试。

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