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1. 发明申请

US20110032978A1 Receiver and Method for Adjusting Adaptive Equalizer of Receiver 有权
标题翻译：用于调整接收机自适应均衡器的接收机和方法
公开(公告)号：US20110032978A1
公开(公告)日：2011-02-10
申请号：US12769905
申请日：2010-04-29
申请人： PO-NIEN LIN , Sterling Smith
发明人： PO-NIEN LIN , Sterling Smith
IPC分类号： H04L27/01
CPC分类号： H04L25/03076
摘要： A receiver includes an adaptive equalizer, a power detecting unit and an adjusting unit. The adaptive equalizer is for receiving a signal and generating an equalized signal. The power detecting unit, coupled to the adaptive equalizer, is for detecting the strength of the equalized signal during a first period to generate a first strength signal, and detecting the strength of the equalized signal during a second period to generate a second strength signal. The adjusting unit, coupled to the power detecting unit and the adaptive equalizer, is for adjusting the compensation strength for the adaptive equalizer according to the first and second strength signals.
摘要翻译：接收机包括自适应均衡器，功率检测单元和调整单元。自适应均衡器用于接收信号并产生均衡的信号。耦合到自适应均衡器的功率检测单元用于在第一周期期间检测均衡信号的强度以产生第一强度信号，并且在第二周期期间检测均衡信号的强度以产生第二强度信号。耦合到功率检测单元和自适应均衡器的调整单元用于根据第一和第二强度信号调整自适应均衡器的补偿强度。

2. 发明授权

US07795937B2 Semi-digital delay locked loop circuit and method 有权
标题翻译：半数字延迟锁相环电路及方法
公开(公告)号：US07795937B2
公开(公告)日：2010-09-14
申请号：US12402815
申请日：2009-03-12
申请人： Sterling Smith , Ellen Chen Yeh , Wen cai Lu
发明人： Sterling Smith , Ellen Chen Yeh , Wen cai Lu
IPC分类号： H03L7/06
CPC分类号： H04N5/126 , H03L7/07 , H03L7/0814 , H03L7/0996
摘要： A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.
摘要翻译：具有自动调整锁定精度的校准机制的可扩展DLL（延迟锁定环路）电路。延迟锁定环电路包括用于根据系统时钟产生多个相位信号的多相锁相环电路，其中相位信号之一是像素时钟; 相位检测器，用于根据像素时钟检测参考信号和反馈信号之间的积分相位误差和分数相位误差; 相位选择器，用于根据分数相位误差选择一个相位信号; 以及延迟电路，用于根据积分相位误差和所选择的相位信号偏移参考信号的相位，以产生输出信号。

3. 发明申请

US20080144358A1 Read state retention circuit and method 有权
标题翻译：读取状态保持电路和方法
公开(公告)号：US20080144358A1
公开(公告)日：2008-06-19
申请号：US11889695
申请日：2007-08-15
申请人： Sterling Smith , Chung-Ho Ning
发明人： Sterling Smith , Chung-Ho Ning
IPC分类号： G11C11/24
CPC分类号： G06K19/0723 , G06K19/0701
摘要： A read state retention circuit and method are disclosed. The read state retention circuit comprises a charge storage unit, charging unit, sensing circuit and state indicator. The charging circuit is coupled to the charge storage unit for charging the charge storage unit. The sensing circuit is coupled to the charge storage unit for sensing a voltage level of the charge storage unit. The state indicator is coupled to the sensing circuit for outputting an indication signal in response to the voltage level.
摘要翻译：公开了一种读取状态保持电路和方法。读取状态保持电路包括电荷存储单元，充电单元，感测电路和状态指示器。充电电路耦合到电荷存储单元以对电荷存储单元进行充电。感测电路耦合到电荷存储单元，用于感测电荷存储单元的电压电平。状态指示器耦合到感测电路，用于响应于电压电平输出指示信号。

4. 发明授权

US07315602B2 Digital spread spectrum frequency synthesizer 有权
标题翻译：数字扩频频率合成器
公开(公告)号：US07315602B2
公开(公告)日：2008-01-01
申请号：US10615845
申请日：2003-07-10
申请人： Sterling Smith
发明人： Sterling Smith
IPC分类号： H03D3/24 , H04B14/06 , H03L25/00 , H03B21/00
CPC分类号： H03L7/16 , H04B1/707
摘要： The present invention provides a digital spread spectrum frequency synthesizer that comprises a noise-shaped quantizer, a divider and an adjustment means. The noise-shaped quantizer is used to quantize a period control word to a time-varying value. The divider is used for generating an output signal by means of dividing a reference signal by the time-varying value, the output signal feeding back to the noise-shaped quantizer so that the noise-shaped quantizer generates the time-varying value in response to the feedback output signal. The adjustment means is used to adjust the period control word by a period offset in response to the output clock. Accordingly, the frequency synthesizer of the present invention can provide a very precise frequency synthesizer featuring a precision spread spectrum clock and jitter stability as well.
摘要翻译：本发明提供了一种数字扩频频率合成器，其包括噪声形量化器，分频器和调整装置。噪声形量化器用于将周期控制字量化到时变值。分频器用于通过将参考信号除以时变值来产生输出信号，该输出信号反馈到噪声形量化器，使得噪声形量化器响应于反馈输出信号。调整装置用于响应于输出时钟调整周期控制字周期偏移。因此，本发明的频率合成器可以提供具有精确扩频时钟和抖动稳定性的非常精确的频率合成器。

5. 发明申请

US20070001999A1 Flat Panel Display Device, Controller, and Method for Displaying Images 有权
标题翻译：平板显示设备，控制器和显示图像的方法
公开(公告)号：US20070001999A1
公开(公告)日：2007-01-04
申请号：US11425719
申请日：2006-06-22
申请人： Sterling Smith , Chih-Tien Chang , Kuo-Feng Hsu , Cheng-Yu Lu , Song-Yi Lin , Guo-Kiang Hung
发明人： Sterling Smith , Chih-Tien Chang , Kuo-Feng Hsu , Cheng-Yu Lu , Song-Yi Lin , Guo-Kiang Hung
IPC分类号： G09G3/36
CPC分类号： G09G3/3406 , G09G3/20 , G09G2310/08 , G09G2320/02 , G09G2320/0233 , G09G2320/064
摘要： A flat panel display device, LCD controller and associated method is provided. The flat panel display device includes a display panel, a lamp for providing a backlight source for the display panel, a power transformation module for providing a power source for the lamp, a non-volatile storage unit for storing program code, and a display controller. The display controller includes an image processing module for processing image data and outputting processed results to the display panel, and a digital pulse width modulation module for adjusting on and off time of the power transformation module with reference to a synchronization signal.
摘要翻译：提供了一种平板显示装置，LCD控制器及相关方法。平板显示装置包括显示面板，用于提供用于显示面板的背光源的灯，用于提供灯的电源的功率变换模块，用于存储程序代码的非易失性存储单元和显示控制器。显示控制器包括用于处理图像数据并将处理结果输出到显示面板的图像处理模块，以及用于参考同步信号调整功率变换模块的接通和关断时间的数字脉宽调制模块。

6. 发明申请

US20060220936A1 APPARATUS AND RELATED METHOD FOR LEVEL CLAMPING CONTROL 有权
标题翻译：用于水平钳位控制的装置和相关方法
公开(公告)号：US20060220936A1
公开(公告)日：2006-10-05
申请号：US11163153
申请日：2005-10-06
申请人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
发明人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
IPC分类号： H03M3/00
CPC分类号： H03M1/1295 , H03L7/08 , H03M1/1255 , H03M1/183 , H04N5/52
摘要： A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.
摘要翻译：提供了电平钳位控制电路和相关电平钳位控制方法。电平钳位控制电路包括参考电平估计器，减法器，钳位运算电路，抖动电路和数模转换器（DAC）。参考电平估计器估计输入信号的参考电平。减法器计算参考电平和期望参考电平之间的差以输出差分信号。钳位计算电路根据差分信号产生第一控制值。抖动电路使第一控制值抖动以交替地输出多个第二控制值。最后，DAC分别利用第二控制值对电容器进行充电或放电来调节输入信号的参考电平。

7. 发明授权

US07095288B2 Logic system with adaptive supply voltage control 有权
标题翻译：具有自适应电源电压控制的逻辑系统
公开(公告)号：US07095288B2
公开(公告)日：2006-08-22
申请号：US10624548
申请日：2003-07-23
申请人： Sterling Smith
发明人： Sterling Smith
IPC分类号： H03B5/04
CPC分类号： H03K19/0016 , H03L7/0802 , H03L7/0816
摘要： A logic system with adaptive supply voltage control comprising a logic circuit clocked by a clock signal from a clock generating circuit and a voltage conversion circuit for generating a dynamically regulated supply voltage for powering the logic circuit. A critical path delay of the logic circuit is designed to be equal to or shorter than a period of the clock signal. The voltage conversion circuit dynamically regulates the supply voltage of the logic circuit based on a bias voltage of the clock generating circuit. According to the invention, the power consumption is effectively minimized while ensuring the logic circuit to function correctly throughout all conditions.
摘要翻译：一种具有自适应电源电压控制的逻辑系统，包括由来自时钟发生电路的时钟信号和电压转换电路提供时钟的逻辑电路，用于产生用于给逻辑电路供电的动态调节的电源电压。逻辑电路的关键路径延迟被设计为等于或短于时钟信号的周期。电压转换电路基于时钟发生电路的偏置电压来动态地调节逻辑电路的电源电压。根据本发明，功率消耗被有效地最小化，同时确保逻辑电路在所有条件下正常工作。

8. 发明申请

US20050270197A1 Video Signal Processing System With A Dynamic ADC Calibration Loop And Related Methods 有权
标题翻译：具有动态ADC校准环路的视频信号处理系统及相关方法
公开(公告)号：US20050270197A1
公开(公告)日：2005-12-08
申请号：US10908741
申请日：2005-05-24
申请人： Sterling Smith , Chia-Ming Yang
发明人： Sterling Smith , Chia-Ming Yang
IPC分类号： G09G3/20 , H03M1/10 , H03M1/12 , H04N5/14
CPC分类号： H03M1/1028 , H03M1/12
摘要： A video signal processing system with a dynamic calibration loop of an ADC comprises a calibration switch for transmitting signals according to a control signal; a reference switch module for transmitting reference voltages according to a plurality of control signals; a reference voltage generator coupled to the reference switch module for providing the reference voltages; a coarse tuner coupled to the calibration switch and the reference switch module for coarse-tuning received signals; an ADC coupled to the coarse tuner for converting analog signals to digital signals; a fine-tuner coupled to the ADC for fine-tuning received signals; and a calibration logic module for controlling the calibration switch, the reference switch module, the coarse tuner, the ADC, and the fine tuner according to signals outputted from the fine tuner, so as to compensate errors of the ADC.
摘要翻译：具有ADC的动态校准环路的视频信号处理系统包括用于根据控制信号发送信号的校准开关; 参考开关模块，用于根据多个控制信号传输参考电压; 耦合到参考开关模块的参考电压发生器，用于提供参考电压; 耦合到校准开关的粗调谐器和用于对接收信号进行粗调的参考开关模块; 耦合到粗调谐器的ADC，用于将模拟信号转换成数字信号; 耦合到ADC的微调器，用于微调接收信号; 以及校准逻辑模块，用于根据从精细调谐器输出的信号来控制校准开关，参考开关模块，粗调谐器，ADC和精细调谐器，以补偿ADC的误差。

9. 发明申请

US20050046491A1 FLEXIBLE SYNTHESIZER FOR MULTIPLYING A CLOCK BY A RATIONAL NUMBER 有权
标题翻译：灵活的合成器，用于通过一个数量来增加时钟
公开(公告)号：US20050046491A1
公开(公告)日：2005-03-03
申请号：US10711175
申请日：2004-08-30
申请人： Sterling Smith
发明人： Sterling Smith
IPC分类号： H03L7/08 , H03L7/16 , H03L7/18 , H03L7/197 , H03L7/00
CPC分类号： H03L7/1976
摘要： A frequency synthesizer that includes two fractional dividers, two noise-shaped quantizers, three integer dividers, a PLL, an algorithm embodied in control logic, and an adjustment means. The noise-shaped quantizers are used to quantize two fractional (fixed-point) values, derived from the divider control words, into time-varying values. The dividers and PLL are used to generate an output signal by means of multiplying a reference signal by the quotient of the divider control word values. Accordingly, the frequency synthesizer of the present invention can provide a very precise output clock, with the average output frequency being the input frequency multiplied by the quotient of the two divider control words, and with high jitter stability.
摘要翻译：一种频率合成器，包括两个分数分频器，两个噪声形量化器，三个整数除法器，PLL，控制逻辑中体现的算法，以及调整装置。噪声量化器用于量化从分频器控制字导出的两个分数（定点）值到时变值。分频器和PLL用于通过将参考信号乘以分频器控制字值的商来产生输出信号。因此，本发明的频率合成器可以提供非常精确的输出时钟，平均输出频率是输入频率乘以两个分频器控制字的商，并具有高抖动稳定性。

10. 发明授权

US06714084B2 High resolution digital controlled oscillator 有权
标题翻译：高分辨率数字控制振荡器
公开(公告)号：US06714084B2
公开(公告)日：2004-03-30
申请号：US10144413
申请日：2002-05-09
申请人： Sterling Smith
发明人： Sterling Smith
IPC分类号： H03B2100
CPC分类号： H03L7/093 , H03K3/0322 , H03L7/0991
摘要： The present invention provides a frequency synthesis circuit. The frequency synthesis circuit includes a noise-shaping quantizer and a digitally controlled oscillator. The noise-shaping quantizer responsive to a plurality of input bits for shaping error signals resulting from the quantization conversion such that most of the error occurs at high frequency. The digitally controlled oscillator is connected to the output of the quantizer having an output frequency responsive to the output of the quantizer.
摘要翻译：本发明提供一种频率合成电路。频率合成电路包括噪声整形量化器和数字控制振荡器。噪声整形量化器响应于多个输入比特，用于整形由量化转换产生的误差信号，使得大部分误差发生在高频。数字控制振荡器连接到具有响应于量化器的输出的输出频率的量化器的输出端。

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