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1. 发明申请

US20060220936A1 APPARATUS AND RELATED METHOD FOR LEVEL CLAMPING CONTROL 有权
标题翻译：用于水平钳位控制的装置和相关方法
公开(公告)号：US20060220936A1
公开(公告)日：2006-10-05
申请号：US11163153
申请日：2005-10-06
申请人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
发明人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
IPC分类号： H03M3/00
CPC分类号： H03M1/1295 , H03L7/08 , H03M1/1255 , H03M1/183 , H04N5/52
摘要： A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.
摘要翻译：提供了电平钳位控制电路和相关电平钳位控制方法。电平钳位控制电路包括参考电平估计器，减法器，钳位运算电路，抖动电路和数模转换器（DAC）。参考电平估计器估计输入信号的参考电平。减法器计算参考电平和期望参考电平之间的差以输出差分信号。钳位计算电路根据差分信号产生第一控制值。抖动电路使第一控制值抖动以交替地输出多个第二控制值。最后，DAC分别利用第二控制值对电容器进行充电或放电来调节输入信号的参考电平。

2. 发明授权

US07486336B2 ADC system, video decoder and related method for decoding composite video signal utilizing clock synchronized to subcarrier of composite video signal 有权
标题翻译： ADC系统，视频解码器及相关方法，利用与复合视频信号副载波同步的复合视频信号进行解码
公开(公告)号：US07486336B2
公开(公告)日：2009-02-03
申请号：US11163127
申请日：2005-10-06
申请人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
发明人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
IPC分类号： H03L7/00
CPC分类号： H03M1/1295 , H03L7/08 , H03M1/1255 , H03M1/183 , H04N5/52
摘要： An analog-to-digital converting system for converting a composite video signal into a digital signal according to a synchronized clock. The analog-to-digital converting system includes an analog-to-digital converter (ADC), a color burst phase estimator and a phase-locked loop (PLL). The ADC converts the composite video signal to the digital signal according to the synchronized clock, wherein the synchronized clock is synchronized to a frequency of a color burst of a chrominance signal of the composite video signal. The color burst phase estimator, coupled to the ADC, estimates the phase of the color burst carried on the composite video signal. The PLL, coupled to the color burst phase estimator, generates the synchronized clock according to the phase of the color burst estimated by the color burst phase estimator.
摘要翻译：一种用于根据同步时钟将复合视频信号转换为数字信号的模拟 - 数字转换系统。模数转换系统包括模数转换器（ADC），色同步相位估计器和锁相环（PLL）。 ADC根据同步时钟将复合视频信号转换为数字信号，其中同步时钟与复合视频信号的色度信号的色同步信号的频率同步。耦合到ADC的色同步相位估计器估计复合视频信号上携带的色同步信号的相位。耦合到色同步相位估计器的PLL根据由色同步相位估计器估计的色同步脉冲的相位产生同步时钟。

3. 发明授权

US07468760B2 Apparatus and related method for level clamping control 有权
标题翻译：电平钳位控制装置及相关方法
公开(公告)号：US07468760B2
公开(公告)日：2008-12-23
申请号：US11163153
申请日：2005-10-06
申请人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
发明人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
IPC分类号： H04N5/18 , H03M1/06
CPC分类号： H03M1/1295 , H03L7/08 , H03M1/1255 , H03M1/183 , H04N5/52
摘要： A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.
摘要翻译：提供了电平钳位控制电路和相关电平钳位控制方法。电平钳位控制电路包括参考电平估计器，减法器，钳位计算电路，抖动电路和数模转换器（DAC）。参考电平估计器估计输入信号的参考电平。减法器计算参考电平和期望参考电平之间的差以输出差分信号。钳位计算电路根据差分信号产生第一控制值。抖动电路使第一控制值抖动以交替地输出多个第二控制值。最后，DAC分别利用第二控制值对电容器进行充电或放电来调节输入信号的参考电平。

4. 发明申请

US20060221243A1 AUTOMATIC GAIN CONTROL ANALOG-TO-DIGITAL CONVERTING SYSTEM AND RELATED METHOD 有权
标题翻译：自动增益控制模拟数字转换系统及相关方法
公开(公告)号：US20060221243A1
公开(公告)日：2006-10-05
申请号：US11163717
申请日：2005-10-28
申请人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
发明人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
IPC分类号： H03M1/12 , H04N5/52
CPC分类号： H03M1/1295 , H03L7/08 , H03M1/1255 , H03M1/183 , H04N5/52
摘要： An analog-to-digital converting system with automatic gain control. The analog-to-digital converting system includes a programmable gain amplifier (PGA) for receiving and amplifying an input signal by a gain factor to generate an amplified input signal; an ADC, coupled to the PGA, for converting the amplified input signal into a digital signal according to an actual reference voltage signal; and an automatic gain controller, coupled to the PGA and the ADC, for jointly controlling the gain factor set to the PGA and the actual reference voltage signal set to the ADC according to a hysteretic behavior.
摘要翻译：具有自动增益控制的模数转换系统。模数转换系统包括用于通过增益因子接收和放大输入信号以产生放大的输入信号的可编程增益放大器（PGA）; 耦合到PGA的ADC，用于根据实际的参考电压信号将放大的输入信号转换成数字信号; 以及耦合到PGA和ADC的自动增益控制器，用于根据迟滞行为共同控制设置到PGA的增益因子和设置到ADC的实际参考电压信号。

5. 发明授权

US07564502B2 Automatic gain control analog-to-digital converting system and related method 有权
标题翻译：自动增益控制模数转换系统及相关方法
公开(公告)号：US07564502B2
公开(公告)日：2009-07-21
申请号：US11163717
申请日：2005-10-28
申请人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
发明人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
IPC分类号： H04N5/52 , H03M1/12
CPC分类号： H03M1/1295 , H03L7/08 , H03M1/1255 , H03M1/183 , H04N5/52
摘要： An analog-to-digital converting system with automatic gain control. The analog-to-digital converting system includes a programmable gain amplifier (PGA) for receiving and amplifying an input signal by a gain factor to generate an amplified input signal; an ADC, coupled to the PGA, for converting the amplified input signal into a digital signal according to an actual reference voltage signal; and an automatic gain controller, coupled to the PGA and the ADC, for jointly controlling the gain factor set to the PGA and the actual reference voltage signal set to the ADC according to a hysteretic behavior.
摘要翻译：具有自动增益控制的模数转换系统。模数转换系统包括用于通过增益因子接收和放大输入信号以产生放大的输入信号的可编程增益放大器（PGA）; 耦合到PGA的ADC，用于根据实际的参考电压信号将放大的输入信号转换成数字信号; 以及耦合到PGA和ADC的自动增益控制器，用于根据迟滞行为共同控制设置到PGA的增益因子和设置到ADC的实际参考电压信号。

6. 发明申请

US20060221242A1 ADC SYSTEM, VIDEO DECODER AND RELATED METHOD FOR DECODING COMPOSITE VIDEO SIGNAL UTILIZING CLOCK SYNCHRONIZED TO SUBCARRIER OF COMPOSITE VIDEO SIGNAL 有权
标题翻译： ADC系统，视频解码器和相关方法，用于解码复合视频信号使用同步到复合视频信号的分组的时钟
公开(公告)号：US20060221242A1
公开(公告)日：2006-10-05
申请号：US11163127
申请日：2005-10-06
申请人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
发明人： Ke-Chiang Huang , Ta-Chan Kao , Sterling Smith
IPC分类号： H03L7/00 , H03M1/12
CPC分类号： H03M1/1295 , H03L7/08 , H03M1/1255 , H03M1/183 , H04N5/52
摘要： An analog-to-digital converting system for converting a composite video signal into a digital signal according to a synchronized clock. The analog-to-digital converting system includes an analog-to-digital converter (ADC), a color burst phase estimator and a phase-locked loop (PLL). The ADC converts the composite video signal to the digital signal according to the synchronized clock, wherein the synchronized clock is synchronized to a frequency of a color burst of a chrominance signal of the composite video signal. The color burst phase estimator, coupled to the ADC, estimates the phase of the color burst carried on the composite video signal. The PLL, coupled to the color burst phase estimator, generates the synchronized clock according to the phase of the color burst estimated by the color burst phase estimator.
摘要翻译：一种用于根据同步时钟将复合视频信号转换为数字信号的模拟 - 数字转换系统。模数转换系统包括模数转换器（ADC），色同步相位估计器和锁相环（PLL）。 ADC根据同步时钟将复合视频信号转换为数字信号，其中同步时钟与复合视频信号的色度信号的色同步信号的频率同步。耦合到ADC的色同步相位估计器估计复合视频信号上携带的色同步信号的相位。耦合到色同步相位估计器的PLL根据由色同步相位估计器估计的色同步脉冲的相位产生同步时钟。

7. 发明授权

US5872480A Programmable down-sampler having plural decimators and modulator using same 失效
标题翻译：具有多个抽取器的可编程下采样器和使用其的调制器
公开(公告)号：US5872480A
公开(公告)日：1999-02-16
申请号：US935561
申请日：1997-09-23
申请人： Ke-Chiang Huang
发明人： Ke-Chiang Huang
IPC分类号： H03H17/06 , H04L27/00 , H04L27/233 , H03M7/00 , H04L27/22
CPC分类号： H03H17/0664 , H03H17/0621 , H04L27/2332 , H03H2218/04 , H03H2218/06 , H04L2027/003 , H04L2027/0057 , H04L7/0029
摘要： A digital QPSK demodulator includes a plurality of two-input-two-output (TITO) two-fold decimators where each TITO two-fold decimator operates at a rate equal to its input data rate. The in-phase I signal and the quadrature Q signal are computed in an interleaved sequence of {Q"(n), I"(n), Q"(n+1), I"(n+1), . . . } to generate Q" decimation output and I" decimation output. The TITO two-fold decimators are cascaded in a reverse order to form a programmable down-sampler which decimates the input data by factors of 1, 2, 4, 8 or more. In a first embodiment, the programmable down-sampler is coupled between a complex multiplier and an interpolator. In a second embodiment, the in-phase and quadrature signals are fed through a complex multiplier, an interpolator, then the programmable down-sampler. In the third embodiment, the in-phase and quadrature signals are fed through an interpolator, a complex multiplier, then the programmable down-sampler.
摘要翻译：数字QPSK解调器包括多个双输入双输出（TITO）双倍抽取器，其中每个TITO双倍抽取器以等于其输入数据速率的速率操作。以{Q“（n），I”（n），Q“（n + 1），I”（n + 1）的交织序列计算同相I信号和正交Q信号，，。。。 }来产生Q“抽取输出和I”抽取输出。 TITO双倍抽取器以相反的顺序级联以形成可编程下采样器，其通过1,2,4,8或更多因子对输入数据进行抽取。在第一实施例中，可编程下采样器耦合在复数乘法器和内插器之间。在第二实施例中，同相和正交信号通过复数乘法器，内插器，然后可编程下采样器馈送。在第三实施例中，同相和正交信号通过内插器，复数乘法器，然后可编程下采样器馈送。

8. 发明授权

US06904084B2 Read channel apparatus and method for an optical storage system 失效
标题翻译：用于光学存储系统的读通道装置和方法
公开(公告)号：US06904084B2
公开(公告)日：2005-06-07
申请号：US09947169
申请日：2001-09-05
申请人： Ke-Chiang Huang , Tzu-Pai Wang
发明人： Ke-Chiang Huang , Tzu-Pai Wang
IPC分类号： G11B20/10 , H04L7/02 , H03H7/40
CPC分类号： H04L7/0029 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/1403
摘要： A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from the optical storage system and subtracts an estimated DC offset from the asynchronous sample values to generate a sequence of asynchronous DC-removed sample values. The asynchronous DC-removed sample values are separately interpolated by two interpolators to generate a sequence of synchronous even-time sample values and a sequence of synchronous odd-time sample values respectively. The synchronous even-time and odd-time sample values are separately equalized by two equalizers in accordance with a target spectrum to generate a sequence of even-time equalized sample values and a sequence of odd-time equalized sample values respectively. A DC offset estimator generates the estimated DC offset from the even-time equalized sample values and the odd-time equalized sample values. The interpolators are under the control of a timing recovery controller for synchronizing the even-time and odd-time sample values to the baud rate. In the preferred embodiment, the recorded data are determined from the even-time equalized sample values and the odd-time equalized sample values.
摘要翻译：公开了一种用于以预定波特率读取记录在光存储系统上的数据的读通道装置。该设备异步地对从光学存储系统产生的模拟读取信号进行采样，并从异步采样值中减去估计的DC偏移，以产生异步DC去除样本值的序列。异步DC去除的采样值由两个内插器分别内插，以分别产生同步偶数采样值序列和同步奇数时间采样值序列。根据目标频谱，两个均衡器分别均衡同步的偶数时间和奇数时间采样值，以分别产生偶数均衡采样值的序列和奇数时间均衡采样值的序列。 DC偏移估计器从偶数均衡采样值和奇数时间均衡采样值产生估计的DC偏移。内插器在定时恢复控制器的控制下，用于将偶数和奇数时间采样值同步到波特率。在优选实施例中，根据偶数均衡采样值和奇数时间均衡采样值确定记录数据。

9. 发明授权

US07447511B2 Method and device for equalizing mode selection 有权
标题翻译：均衡模式选择的方法和装置
公开(公告)号：US07447511B2
公开(公告)日：2008-11-04
申请号：US11140894
申请日：2005-06-01
申请人： Ke-Chiang Huang , Kuo-Feng Hsu , Jiunn-Yih Lee , Hsian-Feng Liu
发明人： Ke-Chiang Huang , Kuo-Feng Hsu , Jiunn-Yih Lee , Hsian-Feng Liu
IPC分类号： H04B7/00
CPC分类号： H04B3/54 , H04B3/56 , H04B2203/5495
摘要： A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes. The device comprises: a programmable equalizer, having a plurality of equalizing modes, receiving an original signal so as to output an equalized signal; a phase-locked loop, receiving a reference clock signal and a first control signal so as to output first sampling pulses and second sampling pulses; a data slicing device, coupled to the phase-locked loop and the programmable equalizer and receiving the first sampling pulses, the second sampling pulses and the equalized signal so as to output a first slicing signal and a second slicing signal; and a signal processing device, coupled to the data slicing device and receiving the first slicing signal and the second slicing signal so as to output the first control signal and a second control signal; wherein the signal processing device programs the programmable equalizer by using the second control signal so as to select an equalizing mode from the plurality of equalizing modes for the programmable equalizer.
摘要翻译：公开了一种均衡模式选择的方法和装置。该方法包括以下步骤：响应于均衡信号提供第一采样脉冲; 提供滞后于所述第一采样脉冲的第二采样脉冲用于对所述均衡信号进行采样的预定相移; 根据第一采样脉冲和第二采样脉冲建立第一观测窗口和第二观测窗口，以确定多个均衡模式中的每一个是好还是坏; 以及在所述多个均衡模式中选择一个均衡模式。该装置包括：具有多个均衡模式的可编程均衡器，接收原始信号以输出均衡信号; 锁相环，接收参考时钟信号和第一控制信号，以便输出第一采样脉冲和第二采样脉冲; 数据切片装置，耦合到锁相环和可编程均衡器，并接收第一采样脉冲，第二采样脉冲和均衡信号，以输出第一限幅信号和第二限幅信号; 以及信号处理装置，耦合到所述数据限幅装置并接收所述第一限幅信号和所述第二限幅信号，以便输出所述第一控制信号和第二控制信号; 其中信号处理装置通过使用第二控制信号来对可编程均衡器进行编程，以从可编程均衡器的多个均衡模式中选择均衡模式。

10. 发明授权

US07212567B2 Read channel apparatus and method for an optical storage system 有权
公开(公告)号：US07212567B2
公开(公告)日：2007-05-01
申请号：US11126991
申请日：2005-05-11
申请人： Ke-Chiang Huang , Tzu-Pai Wang
发明人： Ke-Chiang Huang , Tzu-Pai Wang
IPC分类号： H03H7/40
CPC分类号： H04L7/0029 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/1403
摘要： A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from the optical storage system and subtracts an estimated DC offset from the asynchronous sample values to generate a sequence of asynchronous DC-removed sample values. The asynchronous DC-removed sample values are separately interpolated by two interpolators to generate a sequence of synchronous even-time sample values and a sequence of synchronous odd-time sample values respectively. The synchronous even-time and odd-time sample values are separately equalized by two equalizers in accordance with a target spectrum to generate a sequence of even-time equalized sample values and a sequence of odd-time equalized sample values respectively. A DC offset estimator generates the estimated DC offset from the even-time equalized sample values and the odd-time equalized sample values. The interpolators are under the control of a timing recovery controller for synchronizing the even-time and odd-time sample values to the baud rate. In the preferred embodiment, the recorded data are determined from the even-time equalized sample values and the odd-time equalized sample values.

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