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1. 发明授权

US5440514A Write control for a memory using a delay locked loop 失效
标题翻译：使用延迟锁定环对内存进行写入控制
公开(公告)号：US5440514A
公开(公告)日：1995-08-08
申请号：US207510
申请日：1994-03-08
申请人： Stephen T. Flannagan , Ray Chang , Lawrence F. Childs
发明人： Stephen T. Flannagan , Ray Chang , Lawrence F. Childs
IPC分类号： G11C7/22 , G11C17/10
CPC分类号： G11C7/222 , G11C7/22
摘要： A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.
摘要翻译：存储器（20）包括用于控制存储器（20）的写周期的写控制延迟锁定环（52）。延迟锁定环（52）包括仲裁电路（264），电压控制延迟（VCD）电路（260）和VCD控制电路（265）。仲裁器电路（264）将时钟信号与来自VCD电路（260）的延迟的时钟信号进行比较。作为响应，仲裁器电路（264）向VCD控制电路（265）提供延迟信号。 VCD控制电路（265）接收延迟信号并调整延迟的时钟信号的传播延迟以补偿时钟频率的变化，以及补偿处理，温度和电源变化。

2. 发明授权

US5670815A Layout for noise reduction on a reference voltage 失效
标题翻译：参考电压降噪布局
公开(公告)号：US5670815A
公开(公告)日：1997-09-23
申请号：US270560
申请日：1994-07-05
申请人： Lawrence F. Childs , Stephen T. Flannagan , Ray Chang , Donovan L. Raatz
发明人： Lawrence F. Childs , Stephen T. Flannagan , Ray Chang , Donovan L. Raatz
IPC分类号： H01L23/528 , H01L29/76 , H01L31/062
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： A layout portion (20) has a first portion (25), and a second portion (55). In the first portion (25), a reference voltage line (27) is disposed between two V.sub.DD power supply lines (26, 30) for a first predetermined length, for providing capacitive coupling between V.sub.DD and a reference voltage. In the second portion (55), the reference voltage line (27) is disposed between two V.sub.SS power supply lines (28, 41) for a second predetermined length, for providing capacitive coupling between V.sub.SS and the reference voltage. The capacitive coupling stabilizes the reference voltage with respect to the power supply voltage, and reduces power supply noise due to lead inductance and changing current demand. In addition, the power supply lines (26, 28, 30, 41) are disposed half above an N-type region (22) and half above a P-type substrate (21) for reducing local transistor switching noise.
摘要翻译：布局部分（20）具有第一部分（25）和第二部分（55）。在第一部分（25）中，在两个VDD电源线（26,30）之间以第一预定长度设置参考电压线（27），用于在VDD和参考电压之间提供电容耦合。在第二部分（55）中，参考电压线（27）被设置在两个VSS电源线（28,41）之间的第二预定长度上，用于提供VSS与参考电压之间的电容耦合。电容耦合使参考电压相对于电源电压稳定，并且由于引线电感和电流需求的变化而降低了电源噪声。此外，电源线（26,28,30,41）在N型区域（22）的上方设置一半，并且在P型衬底（21）的上方设置一半以减少局部晶体管开关噪声。

3. 发明授权

US5384737A Pipelined memory having synchronous and asynchronous operating modes 失效
标题翻译：流水线存储器具有同步和异步操作模式
公开(公告)号：US5384737A
公开(公告)日：1995-01-24
申请号：US207509
申请日：1994-03-08
申请人： Lawrence F. Childs , Kenneth W. Jones , Stephen T. Flannagan , Ray Chang
发明人： Lawrence F. Childs , Kenneth W. Jones , Stephen T. Flannagan , Ray Chang
IPC分类号： G11C7/10 , G11C29/14 , G11C13/00
CPC分类号： G11C29/14 , G11C7/1039 , G11C7/1045 , G11C7/1072
摘要： A pipelined memory (20) has a synchronous operating mode and an asynchronous operating mode. The memory (20) includes output registers (34) and output enable registers (48) which are used to electrically switch between the asynchronous operating mode and the synchronous operating mode. In addition, in the synchronous operating mode, the depth of pipelining can be changed between a three stage pipeline and a two stage pipeline. By changing the depth of pipelining, the memory (20) can operate using a greater range of clock frequencies. In addition, the operating frequency can be changed to facilitate testing and debugging of the memory (20).
摘要翻译：流水线存储器（20）具有同步操作模式和异步操作模式。存储器（20）包括用于在异步操作模式和同步操作模式之间电切换的输出寄存器（34）和输出使能寄存器（48）。另外，在同步运行模式中，流水线的深度可以在三段管线和两级管线之间变化。通过改变流水线的深度，存储器（20）可以使用更大的时钟频率范围来操作。另外，可以改变操作频率以便于存储器（20）的测试和调试。

4. 发明授权

US5426381A Latching ECL to CMOS input buffer circuit 失效
标题翻译：将ECL锁存到CMOS输入缓冲电路
公开(公告)号：US5426381A
公开(公告)日：1995-06-20
申请号：US247819
申请日：1994-05-23
申请人： Stephen T. Flannagan , Lawrence F. Childs
发明人： Stephen T. Flannagan , Lawrence F. Childs
IPC分类号： H03K3/356 , H03K19/01
CPC分类号： H03K3/35606 , H03K3/356034 , H03K3/356113
摘要： A latching ECL to CMOS input buffer (20) has an input buffer (21) for receiving an ECL input signal, a CMOS latch (35), and driver circuits (55, 65). Transmission gates (31, 32) are used to couple the input buffer (21) to the latch (35) in response to a CMOS clock signal being a logic low. The driver circuits (55, 65) are coupled to transmission gates (31, 32). While the clock signal is a logic low, input nodes of the first and second driver circuits (55, 65) are precharged to a relatively high voltage in order to isolate the input signal from the first and second driver circuits (55, 65). The latch (35) both latches the logic state of the ECL input signal and converts the ECL input signal to CMOS logic levels. This allows an input signal to be latched and level converted within a relatively short period of time.
摘要翻译： CMOS输入缓冲器（20）的锁存ECL具有用于接收ECL输入信号的输入缓冲器（21），CMOS锁存器（35）和驱动器电路（55,65）。响应于CMOS时钟信号为逻辑低，传输门（31,32）用于将输入缓冲器（21）耦合到锁存器（35）。驱动电路（55,65）耦合到传输门（31,32）。当时钟信号为逻辑低电平时，第一和第二驱动电路（55,65）的输入节点被预充电到较高的电压，以隔离来自第一和第二驱动电路（55,65）的输入信号。锁存器（35）都锁存ECL输入信号的逻辑状态，并将ECL输入信号转换为CMOS逻辑电平。这允许输入信号在相对短的时间段内被锁存和电平转换。

5. 发明授权

US5416744A Memory having bit line load with automatic bit line precharge and equalization 失效
标题翻译：具有自动位线预充电和均衡的位线负载的存储器
公开(公告)号：US5416744A
公开(公告)日：1995-05-16
申请号：US207515
申请日：1994-03-08
申请人： Stephen T. Flannagan , Lawrence F. Childs
发明人： Stephen T. Flannagan , Lawrence F. Childs
IPC分类号： G11C11/41 , G11C7/12 , G11C7/00
CPC分类号： G11C7/12
摘要： A bit line load (380) is coupled to a bit line pair and includes bipolar pull up transistors (389, 403), P-channel load transistors (390, 404), a NAND logic gate (395), and a P-channel equalization transistor. The NAND logic gate (395) senses a differential voltage on the bit line pair, and provides an equalization signal. When a write control signal indicates the end of a write cycle, the equalization signal initiates precharge and equalization of the bit line pair.
摘要翻译：位线负载（380）耦合到位线对，并且包括双极上拉晶体管（389,403），P沟道负载晶体管（390,404），NAND逻辑门（395）和P沟道均衡晶体管。 NAND逻辑门（395）感测位线对上的差分电压，并提供均衡信号。当写控制信号指示写周期结束时，均衡信号启动位线对的预充电和均衡。

6. 发明授权

US5610543A Delay locked loop for detecting the phase difference of two signals having different frequencies 失效
标题翻译：用于检测具有不同频率的两个信号的相位差的延迟锁定环
公开(公告)号：US5610543A
公开(公告)日：1997-03-11
申请号：US417155
申请日：1995-04-04
申请人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
发明人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
IPC分类号： G11C7/22 , H03L7/06 , H03K5/13
CPC分类号： G11C7/22
摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.
摘要翻译：延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步，。塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

7. 发明授权

US6157583A Integrated circuit memory having a fuse detect circuit and method therefor 有权
标题翻译：具有熔丝检测电路的集成电路存储器及其方法
公开(公告)号：US6157583A
公开(公告)日：2000-12-05
申请号：US261876
申请日：1999-03-02
申请人： Glenn E. Starnes , Stephen T. Flannagan , Ray Chang
发明人： Glenn E. Starnes , Stephen T. Flannagan , Ray Chang
IPC分类号： H01L21/82 , G06F11/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C7/00
CPC分类号： G11C29/02 , G06F11/006 , G11C29/44
摘要： Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.
摘要翻译：集成电路存储器（100）中的保险丝和检测电路（124）包括用于检测保险丝（208）的开路状态或闭路状态的铜熔丝（208）和熔丝状态检测级（202）。保险丝检测电路（124）提供对应于熔丝状态的输出信号，并且在检测期间，将熔丝两端的电压降限制为与施加到集成电路存储器的电源电压无关的绝对值。保险丝检测电路（124）在集成电路存储器（100）上电时工作，并且在保险丝的状态被检测和锁存之后被禁用，并且电源足以用于集成电路存储器（100）的可靠运行，。通过限制熔断的铜熔丝（208）上的电压降，潜在的电迁移问题就会降低。

8. 发明授权

US5440515A Delay locked loop for detecting the phase difference of two signals having different frequencies 失效
标题翻译：用于检测具有不同频率的两个信号的相位差的延迟锁定环
公开(公告)号：US5440515A
公开(公告)日：1995-08-08
申请号：US207517
申请日：1994-03-08
申请人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
发明人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
IPC分类号： G11C7/22 , G11C7/00
CPC分类号： G11C7/22
摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.
摘要翻译：延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步，。塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

9. 发明授权

US4964083A Non-address transition detection memory with improved access time 失效
标题翻译：非地址转换检测存储器具有改进的访问时间
公开(公告)号：US4964083A
公开(公告)日：1990-10-16
申请号：US344200
申请日：1989-04-27
申请人： Scott G. Nogle , Stephen T. Flannagan
发明人： Scott G. Nogle , Stephen T. Flannagan
IPC分类号： G11C11/419 , G11C7/06 , G11C7/22 , G11C8/18 , G11C11/409
CPC分类号： G11C7/062 , G11C7/22 , G11C8/18
摘要： A memory which senses output signals from a selected memory cell during a read cycle using a non-address transition detection apparatus. The memory has a plurality of memory cells which provide signals to a pair of bit lines when selected. An input circuit drives word lines and select a bit line pair of a memory cell located at the intersection of a selected word line and a selected bit line pair. The memory cell outputs bit line signals which are sensed by a combination of a differential amplifier, a level shifter, and a transconductance amplifier, and are thereafter output and presented externally at a logic state representative of a differential current at outputs of the transconductance amplifier. The combination sensing apparatus and a method for constructing such an apparatus decrease access time significantly over a prior art memory using address transition detection.

10. 发明授权

US4644196A Tri-state differential amplifier 失效
标题翻译：三态差分放大器
公开(公告)号：US4644196A
公开(公告)日：1987-02-17
申请号：US695643
申请日：1985-01-28
申请人： Stephen T. Flannagan
发明人： Stephen T. Flannagan
IPC分类号： G11C11/56 , H03K5/24 , G11C7/06
CPC分类号： G11C11/5621 , H03K5/2481 , G11C11/412 , G11C7/06
摘要： An amplifier has a pair of common source transistors in which the sources are coupled together during a first mode of operation and isolated from each other during a second mode of operation. A current source provides current between a power supply terminal and these sources during the first mode and prevents current flow therebetween during the second mode. A pair of switchable loads act as loads for the common source transistors during the first mode and are switched off during the second mode.
摘要翻译：放大器具有一对公共源晶体管，其中源在第一操作模式期间耦合在一起，并且在第二操作模式期间彼此隔离。电流源在第一模式期间在电源端子和这些源之间提供电流，并且在第二模式期间防止电流在它们之间流动。在第一模式期间，一对可切换负载用作公共源晶体管的负载，并且在第二模式期间被关断。

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