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1. 发明授权

US5610543A Delay locked loop for detecting the phase difference of two signals having different frequencies 失效
标题翻译：用于检测具有不同频率的两个信号的相位差的延迟锁定环
公开(公告)号：US5610543A
公开(公告)日：1997-03-11
申请号：US417155
申请日：1995-04-04
申请人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
发明人： Ray Chang , Stephen T. Flannagan , Kenneth W. Jones
IPC分类号： G11C7/22 , H03L7/06 , H03K5/13
CPC分类号： G11C7/22
摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.
摘要翻译：延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步，。塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

2. 发明授权

US4964083A Non-address transition detection memory with improved access time 失效
标题翻译：非地址转换检测存储器具有改进的访问时间
公开(公告)号：US4964083A
公开(公告)日：1990-10-16
申请号：US344200
申请日：1989-04-27
申请人： Scott G. Nogle , Stephen T. Flannagan
发明人： Scott G. Nogle , Stephen T. Flannagan
IPC分类号： G11C11/419 , G11C7/06 , G11C7/22 , G11C8/18 , G11C11/409
CPC分类号： G11C7/062 , G11C7/22 , G11C8/18
摘要： A memory which senses output signals from a selected memory cell during a read cycle using a non-address transition detection apparatus. The memory has a plurality of memory cells which provide signals to a pair of bit lines when selected. An input circuit drives word lines and select a bit line pair of a memory cell located at the intersection of a selected word line and a selected bit line pair. The memory cell outputs bit line signals which are sensed by a combination of a differential amplifier, a level shifter, and a transconductance amplifier, and are thereafter output and presented externally at a logic state representative of a differential current at outputs of the transconductance amplifier. The combination sensing apparatus and a method for constructing such an apparatus decrease access time significantly over a prior art memory using address transition detection.

3. 发明授权

US4644196A Tri-state differential amplifier 失效
标题翻译：三态差分放大器
公开(公告)号：US4644196A
公开(公告)日：1987-02-17
申请号：US695643
申请日：1985-01-28
申请人： Stephen T. Flannagan
发明人： Stephen T. Flannagan
IPC分类号： G11C11/56 , H03K5/24 , G11C7/06
CPC分类号： G11C11/5621 , H03K5/2481 , G11C11/412 , G11C7/06
摘要： An amplifier has a pair of common source transistors in which the sources are coupled together during a first mode of operation and isolated from each other during a second mode of operation. A current source provides current between a power supply terminal and these sources during the first mode and prevents current flow therebetween during the second mode. A pair of switchable loads act as loads for the common source transistors during the first mode and are switched off during the second mode.
摘要翻译：放大器具有一对公共源晶体管，其中源在第一操作模式期间耦合在一起，并且在第二操作模式期间彼此隔离。电流源在第一模式期间在电源端子和这些源之间提供电流，并且在第二模式期间防止电流在它们之间流动。在第一模式期间，一对可切换负载用作公共源晶体管的负载，并且在第二模式期间被关断。

4. 发明授权

US4630239A Chip select speed-up circuit for a memory 失效
标题翻译：一个存储器的片选加速电路
公开(公告)号：US4630239A
公开(公告)日：1986-12-16
申请号：US750638
申请日：1985-07-01
申请人： Paul A. Reed , Stephen T. Flannagan
发明人： Paul A. Reed , Stephen T. Flannagan
IPC分类号： G11C11/41 , G11C8/00 , G11C8/18 , G11C11/40
CPC分类号： G11C8/18
摘要： A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to the select mode, these appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such false transition as an actual transition, the detection of address transitions is suppressed for a predetermined delay time following the transition from the select to deselect modes.
摘要翻译：提供了具有选择和取消选择模式的存储器电路。存储电路作为其用于快速访问数据的技术的一部分，包括响应于检测到地址转换而产生脉冲的电路。当存储器电路从取消选择模式切换到选择模式时，即使没有地址转换，这些也是地址转换。为了防止与解释与实际转变相关的这种虚假转变相关联的延迟，在从选择模式转换到取消选择模式之后，预定的延迟时间抑制了地址转换的检测。

5. 发明授权

US6044036A Buffer circuit, memory device, and integrated circuit for receiving digital signals 失效
标题翻译：缓冲电路，存储器件和用于接收数字信号的集成电路
公开(公告)号：US6044036A
公开(公告)日：2000-03-28
申请号：US78159
申请日：1998-05-13
申请人： Stephen T. Flannagan , William R. Weier
发明人： Stephen T. Flannagan , William R. Weier
IPC分类号： G11C7/10 , G11C8/06 , H03K17/041 , G11C8/00
CPC分类号： H03K17/04106 , G11C7/1051 , G11C7/1078 , G11C8/06
摘要： A buffer circuit (60) that includes a current source (74) having an output, the current source to provide a substantially constant current, a first differential amplifier (62), and a second differential amplifier (66). The current from current source 74 is shared by the first (62) and second (64) differential amplifiers.
摘要翻译：一种缓冲电路（60），包括具有输出的电流源（74），用于提供基本恒定电流的电流源，第一差分放大器（62）和第二差分放大器（66）。来自电流源74的电流由第一（62）和第二（64）差分放大器共用。

6. 发明授权

US5426381A Latching ECL to CMOS input buffer circuit 失效
标题翻译：将ECL锁存到CMOS输入缓冲电路
公开(公告)号：US5426381A
公开(公告)日：1995-06-20
申请号：US247819
申请日：1994-05-23
申请人： Stephen T. Flannagan , Lawrence F. Childs
发明人： Stephen T. Flannagan , Lawrence F. Childs
IPC分类号： H03K3/356 , H03K19/01
CPC分类号： H03K3/35606 , H03K3/356034 , H03K3/356113
摘要： A latching ECL to CMOS input buffer (20) has an input buffer (21) for receiving an ECL input signal, a CMOS latch (35), and driver circuits (55, 65). Transmission gates (31, 32) are used to couple the input buffer (21) to the latch (35) in response to a CMOS clock signal being a logic low. The driver circuits (55, 65) are coupled to transmission gates (31, 32). While the clock signal is a logic low, input nodes of the first and second driver circuits (55, 65) are precharged to a relatively high voltage in order to isolate the input signal from the first and second driver circuits (55, 65). The latch (35) both latches the logic state of the ECL input signal and converts the ECL input signal to CMOS logic levels. This allows an input signal to be latched and level converted within a relatively short period of time.
摘要翻译： CMOS输入缓冲器（20）的锁存ECL具有用于接收ECL输入信号的输入缓冲器（21），CMOS锁存器（35）和驱动器电路（55,65）。响应于CMOS时钟信号为逻辑低，传输门（31,32）用于将输入缓冲器（21）耦合到锁存器（35）。驱动电路（55,65）耦合到传输门（31,32）。当时钟信号为逻辑低电平时，第一和第二驱动电路（55,65）的输入节点被预充电到较高的电压，以隔离来自第一和第二驱动电路（55,65）的输入信号。锁存器（35）都锁存ECL输入信号的逻辑状态，并将ECL输入信号转换为CMOS逻辑电平。这允许输入信号在相对短的时间段内被锁存和电平转换。

7. 发明授权

US4807198A Memory input buffer with hysteresis and dc margin 失效
标题翻译：具有滞后和直流裕度的存储器输入缓冲器
公开(公告)号：US4807198A
公开(公告)日：1989-02-21
申请号：US138103
申请日：1987-12-28
申请人： Stephen T. Flannagan , Peter H. Voss
发明人： Stephen T. Flannagan , Peter H. Voss
IPC分类号： G11C8/06 , G11C11/40 , G11C13/00
CPC分类号： G11C8/06
摘要： A memory has input buffer circuit which provides high immunity to problems associated with address float while providing high speed for both decoder selection and for transition detection. The input buffer circuit includes a pair of input NOR gates which provides for independent signal paths to a cross-coupled latch. Independent hysteresis circuits are provided to each signal path between the two NOR gates and the cross-coupled latch. This allows for independently selecting the amount of dc margin and hysteresis so that the use of hysteresis does not adversely effect dc margin.
摘要翻译：存储器具有输入缓冲电路，其对与地址浮动相关的问题提供高抗扰性，同时为解码器选择和转换检测提供高速度。输入缓冲器电路包括一对输入NOR门，其提供到交叉耦合锁存器的独立信号路径。独立的滞后电路被提供给两个或非门和交叉耦合的锁存器之间的每个信号路径。这允许独立地选择直流余量和滞后量，使得滞后的使用不会不利地影响直流裕度。

8. 发明授权

US4763303A Write-drive data controller 失效
标题翻译：写驱动数据控制器
公开(公告)号：US4763303A
公开(公告)日：1988-08-09
申请号：US832607
申请日：1986-02-24
申请人： Stephen T. Flannagan
发明人： Stephen T. Flannagan
IPC分类号： G11C7/10 , G11C7/00 , G11C11/34
CPC分类号： G11C7/1093 , G11C7/1078 , G11C7/1087
摘要： A write drive data control circuit for controlling the transmission of data to a memory array includes data input means for receiving complimentary data signals which are then transmitted to output circuits. The valid data is latched and the input circuits disabled. The output circuits remain enabled so as to pass the latched data to the memory array. After a predetermined period of time, the output circuits are disabled. In this manner, both the data set up time and data hold time may be independently optimized.
摘要翻译：用于控制向存储器阵列传输数据的写入驱动数据控制电路包括用于接收随后传送到输出电路的互补数据信号的数据输入装置。锁存有效数据，并禁用输入电路。输出电路保持使能，以便将锁存的数据传送到存储器阵列。在预定的时间段之后，输出电路被禁用。以这种方式，可以独立地优化数据建立时间和数据保持时间。

9. 发明授权

US4716302A Identity circuit for an integrated circuit using a fuse and transistor enabled by a power-on reset signal 失效
标题翻译：使用通过上电复位信号使能的保险丝和晶体管的集成电路的标识电路
公开(公告)号：US4716302A
公开(公告)日：1987-12-29
申请号：US945253
申请日：1986-12-22
申请人： Stephen T. Flannagan , Lawrence J. Day , Barry A. Simon
发明人： Stephen T. Flannagan , Lawrence J. Day , Barry A. Simon
IPC分类号： H03K17/18
CPC分类号： H03K17/18 , H01L2223/5444
摘要： An integrated circuit has an identifying circuit coupled to an input. The input has ESD protection. The identifying circuit has a fuse which is in one of two possible states to provide the identifying information. A power on reset circuit provides a pulse in response to application of power to the integrated circuit. A current path between a power supply terminal and the input is provided in response to the power on reset pulse when the fuse is in one state. This current path is blocked when the fuse is in the other state. A user is thus provided with identifying information by the presence or absence of a current path at the input at the time when power is applied.
摘要翻译：集成电路具有耦合到输入的识别电路。输入有ESD保护。识别电路具有处于两种可能状态之一以提供识别信息的熔丝。上电复位电路响应于向集成电路施加电力而提供脉冲。当保险丝处于一个状态时，响应于上电复位脉冲提供电源端子和输入端之间的电流通路。当保险丝处于另一状态时，该电流路径被阻塞。因此，通过在施加电力时在输入端存在或不存在当前路径，向用户提供识别信息。

10. 发明授权

US4453237A Multiple bit output dynamic random-access memory 失效
标题翻译：多位输出动态随机存取存储器
公开(公告)号：US4453237A
公开(公告)日：1984-06-05
申请号：US483772
申请日：1983-04-11
申请人： Edmund A. Reese , Dieter W. Spaderna , Stephen T. Flannagan
发明人： Edmund A. Reese , Dieter W. Spaderna , Stephen T. Flannagan
IPC分类号： G11C11/406 , G11C11/56 , G11C29/00 , G11C29/02 , G11C11/40
CPC分类号： G11C29/80 , G11C11/406 , G11C11/565 , G11C29/02 , G11C7/04
摘要： A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.
摘要翻译：描述了一种动态MOS随机存取存储器，其包括用于允许检查片上刷新计数器的电路。存储器还包括刷新发生器，其频率自动变化以补偿温度变化。其他创新包括仲裁电路，隐藏刷新功能和冗余线路的独特访问。

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